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VLSI Implementation of Video Watermarking for Secure HEVC Coding Standard
Published in S. Ramakrishnan, Cryptographic and Information Security, 2018
The proposed watermarking algorithm is initially simulated by MATLAB to validate the performance. The architecture of proposed system is subsequently implemented on hardware to measure the real-time performance. The hardware performance of proposed algorithm is demonstrated with FPGA prototyping and ASIC Implementation. FPGAs have high speed processing and reconfigurability. Therefore, the proof of concept is verified by FPGA. ASIC implementation is an efficient approach to having a small and dedicated watermarking module as an integral part of portable consumer devices for example camcorder, mobile camera, digital camera or any other similar multimedia devices. This is helpful to embed the real-time watermarking in terms of custom hardware, which is available at electronic appliances and inserts the watermark when video is being captured. The proposed algorithm may be used as an embedding unit which should be an integral part of HEVC encoder. The choice of the hardware implementation either on FPGA or as ASIC chip depends mainly on power requirement, cost and speed. The results are first endorsed on MATLAB platform to verify the essential requirements for ownership verification method. Later on, the proposed algorithm is realized on hardware platform.
Field Programmable Gate Arrays
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
FPGAs have been around since the mid-1980s. Since the mid-1990s, they have increasingly been applied to high performance embedded systems. There are many reasons for FPGAs’ growing popularity. As the number of transistors that can be integrated onto a device has grown, FPGAs have been able to implement denser designs and thus higher performance applications. At the same time, the cost of ASICs has risen dramatically. Most of the cost of manufacturing an ASIC is in the generation of a mask set and in the fabrication (see Chapter 9). Of course, an FPGA is also an ASIC and requires mask sets and fabrication. However, since the cost of an FPGA is amortized over many designs, FPGAs can provide high performance at a fraction of the cost of a state-of-the-art ASIC design. This reusability is due to the main architectural distinction of FPGAs: an FPGA can be configured to implement different designs at different times. While this reconfigurability introduces increased overhead, a good rule of thumb is that an FPGA implemented in the latest logic family has the potential to provide the same level of performance as an ASIC implemented in the technology of one previous generation. Thus, FPGAs can provide high performance while being cost-effective and reprogrammable.
Industrial Electronics Applications of FPGAs
Published in Juan José Rodríguez Andina, Eduardo de la Torre Arnanz, María Dolores Valdés Peña, FPGAs, 2017
Juan José Rodríguez Andina, Eduardo de la Torre Arnanz, María Dolores Valdés Peña
From all that has been discussed in previous chapters, it is evident that FPGA vendors are continuously devoting efforts to include in their devices new features, or improvements to existing ones (as well as in their design tools), aiming at an increasing penetration in the digital design market. Today, FPGAs are used in many different industrial applications because of their high speed and flexibility, inherent parallelism, good cost–performance trade-off, and huge variety of available specialized logic resources. As a consequence, they have been extensively analyzed over the years from the perspective of industrial electronics (Monmasson and Cirstea 2007, 2013; Naouar et al. 2007; Rodriguez-Andina et al. 2007, 2015; Monmasson et al. 2011a,b; Gomes et al. 2013; Gomes and Rodriguez-Andina 2013).
Speed and Accuracy Trade-off ANN/SVM Based Sleep Apnea Detection with FPGA Implementation
Published in Computer Methods in Biomechanics and Biomedical Engineering: Imaging & Visualization, 2023
Talal Bonny, Mahmmud Qatmh, Khaled Obaideen, Maryam Nooman AlMallahi, Mohammad Al-Shabi, Ahmed Al-Shammaa
The proposed method can help overcome some of the limitations by using AI to decocted the sleep apnoea in the following ways: Speed: FPGAs are hardware devices that can be programmed to perform specific tasks with high speed and low latency. This can enable real-time processing of sleep apnoea data, which is critical for clinical applications.Efficiency: ANNs and SVMs are machine learning algorithms that can be optimised to process large amounts of data with high accuracy and efficiency. This can help overcome the limitations of small sample sizes and lack of diversity in patient populations by training the algorithms on large and diverse datasets.Flexibility: FPGAs are highly configurable and can be programmed to perform a wide range of tasks. This makes them ideal for processing different types of sleep apnoea data, such as EEG, ECG, and respiratory signals.Real-world testing: The use of FPGAs, ANNs, and SVMs can help overcome the limitation of lack of real-world testing by enabling the deployment of AI models in real-time clinical settings. This can help evaluate the effectiveness of these models in real-world conditions and improve their generalisability.
17-Level Quasi Z-Source Cascaded MI Topology Interfaced PV System: A Hybrid Technique
Published in IETE Journal of Research, 2023
Sankar P, A. Sheela, S. Albert Alexander
For the switches S1 to S8, a 4 kHz clock is used and turn them ON. Based on the switching angles and modulation index, the switching angle finder determines the ON and OFF times of the switches. The switching pulse generator’s purpose is to produce pulses based on the switching time for all switches, the 17-level QZS cascaded H-bridge multilevel inverter VHDL design has been synthesized for the SPARTON3E500 FPGA system. The speed, area, and power dissipation are important parameters in FPGA design. There are two sorts of power dissipation: a) static power and b) Dynamic power dissipation. This architecture dissipates 85 mW in static power and 25 mW in dynamic power dissipation. The Hardware output voltage of a 17-level CHB multilevel inverter is shown in Figure 19. The Hardware Output current of the 17-level QZS-CMI is shown in Figure 20. The comparison between experimental and simulated THD results is shown in Table 6.
Development of a Signal Processing Software for Scintillation Detectors and Implementation on an FPGA for Fast Sensing
Published in Nuclear Technology, 2023
Benjamin Wellons, Rishya Sankar Kumaran, Sanghun Lee, Shikha Prasad
Field programmable gate arrays have become increasingly useful in the field of radiation detection. Especially when it comes to on-the-fly processing tools, FPGAs are comparatively flexible, cost effective, easier to design, and have fast processing times.6 Many publications have discussed the implementation of FPGAs. In one such publication, Klein and Schmidt7 provide a scope similar to our paper that details the CASCADE detector, a solid converter gas detector using several gas electron multiplier foils as charge-transparent substrates to carry solid10 B layers, that is designed for high-flux neutron applications (107 n/cm2 s) with high demands on the dynamic range and contrast, as well as background. The CASCADE detector uses an application-specific integrated circuit (ASIC) electronic front end paired with an adaptable integrated FPGA data processing unit to provide high rate capacity and real-time event reconstruction.7 In their set configuration, each module was able to detect 106 neutrons per second with 10% dead time. The FPGA recorded data at 10 MHz (each data counter had a depth of 32 bits) extracting pulse height values.