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Semi-custom devices, programmable logic and device technology
Published in D.A. Bradley, N.C. Burd, D. Dawson, A.J. Loader, Mechatronics, 2018
D.A. Bradley, N.C. Burd, D. Dawson, A.J. Loader
The common denominator for all logic circuit designs is the logic gate, and any logic function can be created entirely of either logic NAND gates or logic NOR gates. The gate array is simply an array of logic gates which has been fabricated as far as the final step in the process, which defines the interconnection of the individual gates on the array. It is the responsibility of the circuit designer to define the interconnection between the gates, and therefore to define the function of the gate array. The advantage of this approach is that the fabrication on the uncommitted chip is almost complete, and the time to finish the manufacture of the final device when the design is complete will therefore be shorter than for a full custom device, which has to go through all stages of the fabrication process once the design is finished.
Introduction
Published in M. Michael Vai, Vlsi Design, 2017
Since all layers other than the metal layers in a gate-array are prefabricated, the turn-around time, defined as the time elapsed between the submission of a design and the receipt of chips, is reduced. The cost of a gate-array is also lower than that of a full-custom chip since gate-arrays can be mass produced and used in many different designs. Only a small number of processing steps are involved in a personalization. Another non-trivial advantage of gate-arrays is that they are often manufactured with the most advanced technology (see Problem 1.12). However, designs using gate-arrays are more restrictive than full-custom designs since all transistors are of fixed sizes.
Electronic Components
Published in Michael Pecht, Handbook of Electronic Package Design, 2018
Denise Burkus Harris, Michael Pecht, Pradeep Lall
In applications where high packing density and large flexibility combined with high volume are needed, gate array carriers are often used whereby prefabricated gates are connected according to the needs of the customer. Gate arrays are a class of integrated circuits which provide integration of standard logic circuits. Gate arrays are used when more complex integrated circuits are not available or a customized circuit is too expensive. The gate arrays offer high packaging density, no system redesign, high reliability, and short turnaround time.
An overview of self-engineering systems
Published in Journal of Engineering Design, 2021
Electronics component designers have, for a long time, exploited the ability of reconfiguration and redundancy to make fault-tolerant systems. One of the early solutions (from the 1980s) is a field-programmable gate array (FPGA), which contains programmable logic blocks and memory elements which can be reconfigured when needed. FPGAs offer a cheaper solution than having a complete redundant system which can quickly lead to spiralling costs (Frei et al. 2013). FPGAs and other evolvable hardware have been extensively researched by previous authors (Zhang et al. 2016). Other authors repaired random access memory (RAM) devices with reconfiguration; faulty memory cells are identified using a memory test (monitoring storage and change of data in cells), data in a faulty memory cell is stored at new spare addresses and the system self-reconfigures to adapt to the change (Nair and Bonifus 2018; Shvydun and Adham 2014). The repair ability of these systems is limited by the availability of redundant parts. Diagnosing faulty cells can be difficult in a complex system, a Built-in Self-testing (BIST) system is often used in electronics to identify faulty cells or parts (Bell et al. 2013).
GMMSO: game model-combined improved moth search optimization approach for reconfigurable asymmetric multi-processor system-on-chip architecture
Published in Engineering Optimization, 2023
Isaivani Mariyappan, Malathi Veluchamy
Very large-scale integration (VLSI) circuits are becoming more sophisticated day by day, and the multi-processor system-on-chip (MPSoC) is one such technology in advanced VLSI systems. In general, the MPSoC architecture embodies numerous processing elements and essential system components for the specific application to carry out the demands of embedded applications (Wolf, Jerraya, and Martin 2008). Tailoring the computational platform based on the specific requirements would reduce the complications in the VLSI area, and this can be achieved by implementing heterogeneous MPSoCs and specialized hardware accelerators (HWAs). Such accelerators take advantage of the parallelism property of particular applications and thus expedite the execution of defined tasks better than any general-purpose system architecture. The field programmable gate array (FPGA) is a developing technology that sets out an incredibly flexible platform through its superior reconfigurable ability. Owing to the generous capacity of FPGAs, the complete MPSoC circuit is implemented in a single FPGA device (Ma, Huang, and Andrews 2012). The asymmetric heterogeneous multi-processor systems-on-chip (AHt-MPSoC) configuration ensures the effective exploitation of hardware resources to deliver superior performance while consuming less power. Nevertheless, their usage leads to a larger design space of various possible system arrangements, which ultimately necessitates an appropriate design space exploration (DSE) tool to identify the best configuration based on application needs. The optimization of resource utilization becomes a crucial process in the system configuration, which can be achieved by applying optimization algorithms.