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Field Programmable Gate Arrays
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
An application-specific integrated circuit (ASIC) is an integrated circuit customized for a particular use, and frequently is part of an embedded system. ASICs are designed using computer-aided design (CAD) tools and then fabricated at a foundry. A field programmable gate array (FPGA) can be viewed as a platform for implementing ASIC designs that does not require fabrication. FPGAs can be customized “in the field,” hence the name. While the design flow for ASICs and that for FPGAs are similar, the underlying computational structures are very different. Designing an ASIC involves implementing a design with transistors. An FPGA provides structures that can be “programmed” to implement many of the same functions as on a digital ASIC. The transistors on an FPGA have already been designed to implement these structures. FPGAs are based on memory technology that can be written to reconfigure the device in order to implement different designs. A pattern of bits, called a bitstream, is downloaded to the memory structures on the device to implement a specific design.
Design of a Low-Cost Underwater Acoustic Modem
Published in Krzysztof Iniewski, Optical, Acoustic, Magnetic, and Mechanical Sensor Technologies, 2017
An ASIC is custom-designed for a particular application, with as much system functionality implemented on a single die. ASICs offer exceptional performance, small size, and low power as they optimize transistor use and clock cycles at the expense of flexibility. They have been shown to offer power consumption 20 times [48] lower than any competing platform [49] ASICs have a long time to market and high nonrecurring engineering costs making them practical only for high-volume production or for designs that demand extremely tight size and power requirements. To the best of our knowledge, no ASIC underwater acoustic modem exists.
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Published in Phillip A. Laplante, Dictionary of Computer Science, Engineering, and Technology, 2017
application-specific integrated circuit (ASIC) in the broadest sense, integrated circuits that are designed for a specific application. The term is used to describe VLSI circuits of standard form which can be configured either in manufacture or on site to meet the specific needs of the application. The configuration process is generally so inexpensive that such circuits are economical to produce in extremely small runs.
A Review on HT Attacks in PLD and ASIC Designs with Potential Defence Solutions
Published in IETE Technical Review, 2018
G. Sumathi, L. Srivani, D. Thirugnana Murthy, K. Madhusoodanan, S.A.V. Satya Murty
ASICs are customised chips which are designed and manufactured for a specific functionality. In contrast to PLDs, the chip designer, and the customer is one and the same in most of the ASIC-based applications. As a result, the entire life cycle of ASICs can be classified as (i) Customisation phase, and (ii) Post-customisation phase as shown in Figure 1. Here, it is evident that the customisation phase of ASIC is nothing but the combination of pre-customisation and customisation phases of PLDs. The simplified ASIC design flow starts from HDL coding, synthesis, simulation, layout generation, chip fabrication, and finally post-silicon testing. Here, synthesis does netlist generation by compiling and mapping into standard macro cells, whereas layout stage creates graphic database system (GDS-II) design file. Afterwards, GDS-II files are outsourced to foundries for mask preparation and die fabrication as explained in Figure 1. Furthermore, packaging and post-manufacturing testing are carried out before supplying the devices to chip designers. Later on, ICs are integrated with systems and implemented in the field, and this stage is categorised under post-customisation phase.
A hardware intelligent processing accelerator for domestic service robots
Published in Advanced Robotics, 2020
Yutaro Ishida, Takashi Morie, Hakaru Tamukoh
ASICs have an advantage over FPGAs with regards to computing performance and power consumption. In addition, for mass-produced applications, ASICs are also advantageous regarding cost compared to FPGAs. Since ASICs cannot be reconfigured, they cannot update an application after it has been implemented in a robot.
Automated trading systems statistical and machine learning methods and hardware implementation: a survey
Published in Enterprise Information Systems, 2019
Boming Huang, Yuxiang Huan, Li Da Xu, Lirong Zheng, Zhuo Zou
In addition to the algorithm optimization strategy, an important method for reducing system latency is to alleviate the latency generated by the operating system protocol stack. We can achieve this goal by using customized Network Interface Cards (NIC) embedded with specified software that bypass the OS kernel and network stack and improve the latency from 15–20 µs (Morris, Thomas, and Luk 2009) on a half round trip across the stack within an unoptimized system to 4 µs (Subramoni et al. 2010). This method is also known as a standard software solution, and it dramatically lowers the latency by almost 90 percent. Better methods are implemented on hardware-based systems, typically via the usage of Application-Specific Integrated Circuits (ASICs), Graphic Processing Units (GPUs), or Field-Programmable Gate Arrays (FPGAs). GPUs demonstrate great strengths in meeting the needs of strategies that demand complex parallel computing and large throughput, although GPUs fail to supply sufficient low latency because of the deep pipelines (Lockwood et al. 2012). ASIC may lack flexibility and is always accompanied with a much higher cost in terms of long design cycles and expensive expert labor. Among the devices mentioned above, FPGA is the most promising option to date, as shown in Figure 2. The advantages of FPGA include a reconfigurable framework, shorter time-to-market, lower engineering cost, and high throughput; thus, FPGA has led to great performance in the acceleration of financial applications. Most of the earlier work on FPGA acceleration (Morris, Thomas, and Luk 2009; Herrmann et al. 2009) was concentrated on UDP/IP handling because this procedure is responsible for most of the latency in ordinary PC-based systems generated by CPU interrupts and unpredictable PCIe transfers. In Leber, Geib, and Litz (2011), a microcode engine was proposed to decode multiple templates of the FAST protocol distributed by different exchanges, and this engine offloads both UDP/IP and FAST decoding to the FPGA and decreases the half-round latency from 4.1 µs to 2.6 µs. Lobo et al. (2012) introduced a library of prebuilt FPGA IP blocks provided by Algo-Logic and observed a round-trip latency of only 1 µs with a trading algorithm built inside. The library is intended for protocol optimization to allow clients to build their applications without having to consider the total fundamental infrastructure. This method has shortened the development cycle to an extent. Tang et al. (2016) presented a scalable FPGA-based architecture to accelerate Chinese A-share data processing.