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Boolean Algebra and Logic Gates
Published in Dale Patrick, Stephen Fardo, Vigyan ‘Vigs’ Chandra, Electronic Digital System Fundamentals, 2020
Dale Patrick, Stephen Fardo, Vigyan ‘Vigs’ Chandra
Boolean expressions are frequently used to describe how a logic circuit operates. We have used these expressions to construct circuits and to define operations. A logic circuit has several alternatives that must be taken into account when evaluating its operation. A graphic display of the operational steps and all its possible alternatives is sometimes needed to understand fully the operation of an expression. A display that shows these operations is called a truth table. A truth table is defined as a tabular listing of all the possible logic-level combinations produced by the input and output of a digital circuit. This means that a truth table is a specifications sheet that describes the exact behavior of a logic circuit. The circuit can have several inputs and one or more outputs.
Components and Devices
Published in Katsuyuki Sakuma, Krzysztof Iniewski, Flexible, Wearable, and Stretchable Electronics, 2020
The simplest implementations of a digital circuit are logic gates. These are the building blocks of all further digital circuits and are an electronic representation of Boolean logic. There are a number of ways to achieve logic gates electronically, the choice of which depends on the available components, in particular the transistor. Common families of logic gates are PMOS, NMOS or CMOS, referring to the use of p-type semiconductor devices, n-type semiconductor devices or combinations of the two (complementary), respectively. Note that the MOS (metal-oxide-semiconductor) acronym is not always technically correct for TFTs; however, the term is still commonly used. PMOS and NMOS logics are simpler to manufacture, at the cost of higher static power dissipation compared to CMOS logic. Due to fabrication and stability challenges, most demonstrated flexible circuits have used either PMOS or NMOS logic. Most logic gates require between one and four transistors. These gates can then be used to construct exponentially more complex circuits, with a corresponding increase in transistor count. Note that designing fault tolerance into a circuit increases the transistor count further. This poses a significant challenge for flexible electronics as it stands today, as obtaining a high yield of consistent devices is difficult.
Functional Logics
Published in Michael Olorunfunmi Kolawole, Electronics, 2020
Combinational logic circuits: Combinational circuits are stateless, whose outputs are functions only of the inputs. Implicitly, a digital circuit is combinational if it produces an output that is a Boolean function (combination) of the input values or variables only. Their circuits are made up of gates, which primarily do not have any feedback; that is, outputs are not connected to inputs. A block diagram of combinational circuits is shown in Figure 2.11. The circuits shown in Figures 2.9 and 2.10 can be described as combinational. Combinational circuits have no capacity for storing information.
An Online Course Content for Undergraduate Students on Full-Custom Design of a Digital VLSI Circuit Using Open-Source Software
Published in IETE Journal of Education, 2023
A CMOS digital circuit implements a complement logic function, for example, CMOS-based NAND gate is a complement of AND function, and CMOS-based NOR gate is a complement of OR function. It is noteworthy that the NAND-NOR comprises a PULL-UP network (realized by pMOS which passes strong 1-logic, i.e. VDD) and PULL-DOWN network (realized by nMOS which passes strong 0-logic, i.e. Ground). The PULL-UP networks are required to charge the output node to VDD. Whereas PULL-DOWN networks are needed to discharge the output node to the Ground. In this way the output node of a digital gate swings between VDD and Ground giving strong logic. A strong logic is a signal when it approaches near power supplies or rails (i.e. VDD and Ground). Under such conditions, the signal can source or sink maximum current.
Quantum Dot Cellular Automata-Based Scan Flip-Flop and Boundary Scan Register
Published in IETE Journal of Research, 2023
Nehru Kandasamy, Firdous Ahmad, D. Ajitha, Balwinder Raj, Nagarjuna Telagam
Multiplexer is a familiarized digital circuit that performs any logic function. The multiplexer consists of 2n inputs, n select lines and one output. This transfer one of inputs to the output depending on the select lines. Here, the conventional rotating 2:1 Multiplexer presented in [32] (Figure 8) has been further modified to design an efficient multiplexer. The conventional design has less polarized output signal, which is predicted in the distorted simulation results, as shown in Figure 8(b). The logic term of the proposed 2:1 MUX in QCA majority output is worked out using Equation (3). To get the fault-free signal, we append some additional cells. Although the new rotating 2:1 multiplexer design has more cells, consumes more area and slower in comparison to [32], it is a practical design and it works in complex circuit. The proposed 2:1 multiplexer design consists of circuit complexity of 23 cells, area of 0.02 μm2 and latency of 0.5 clock cycles. However, the proposed design is more efficient than [33–37]. The results of the comparison of the existing 2:1 multiplexer are presented in Table 5. The proposed 2:1 mux QCA layout and its simulation results are shown in Figure 8(a), respectively.
Sensitivity of SET Pulse-Width and Propagation to Radiation Track Parameters in CMOS Inverter Chain
Published in IETE Journal of Research, 2022
Single-event transient is one of the key reliability issues for electronic systems operated in radiation environment [1–6]. When the single-event transient (SET) is generated in a digital circuit, it propagates through the combinational logic circuitry and gets latched in a storage cell if it arrives during the latching edge of the clock [7]. In combinational circuit, the charge required to store a logic state on a circuit node depends on the nodal capacitance [8]. Due to technology scaling, the nodal capacitance decreases and thereby higher operating speed is achieved. However, this decrease in nodal capacitance reduces the charge required to store a logic state on the node. This leads to the reduction of the critical charge that is responsible to create a SET in the circuit, thereby increasing the circuit's SET vulnerability. Thus, in sub-50 nm devices, the SET vulnerability is more due to reduction of nodal capacitance. The SET pulse generated at a node will also get modified during propagation either by getting attenuated or broadened. Hence, a thorough analysis is required to understand the SET pulse-width and propagation in circuits designed with sub-50 nm devices and its dependence on radiation parameters.