China
Africa
Explore chapters and articles related to this topic
Digital Logic Families
Published in Jerry C. Whitaker, Microelectronics, 2018
There is no universally accepted dividing line between complex PLDs and FPGAs. Not only do architectures differ from manufacturer to manufacturer, the method of interconnect programming also differs. The term complex programmable logic device (CPLD) generally denotes devices organized as large arrays of PAL macrocells, with fixed delay feedback of macrocells outputs into the AND–OR array (Fig. 7.16). CLPD time delays are more predictable than those of FPGAs, which can make them simpler to design with. A more important distinction between CPLDs and FPGAs is the ratio of combinatorial logic to sequential logic in their logic cells. The PAL-like structure of CPLDs means that the flip-flop in each logic macrocell is fed by the logical sum of several logical products. The products can include a large number of input and feedback signals. Thus, CPLDs are well suited to applications such as state machines that have logic functions including many variables. FPGAs, on the other hand, tend toward cells that include a flip-flop driven by a logic function of only three or so variables and are better suited to situations requiring many registers fed by relatively simple functions.
Digital Design with Programmable Logic Devices
Published in Suman Lata Tripathi, Sobhit Saxena, Sushanta Kumar Mohapatra, Advanced VLSI Design and Testability Issues, 2020
M. Panigrahy, S. Jena, R. L. Pradhan
In general, a CPLD may be viewed to have a number of logic blocks, a dedicated I/O block and a switch matrix interconnecting them. I/O block consists of I/O elements that provide buffering for the input and output signals. The logic block is formed by several logic elements known as macrocells. A macrocell comprises AND and OR arrays, a dedicated flip-flop, and control signals for implementation of the desired combinatorial or sequential functions. Fast routing between macrocells leads to lower time delays within a logic block. Dedicated global clock lines leverage proper clock distribution among logic blocks and uniform timing properties. The modern CPLDs contain 32–1700 macrocells enabling designers to implement complex logic functions.
Advanced Digital Concepts
Published in Dale Patrick, Stephen Fardo, Vigyan ‘Vigs’ Chandra, Electronic Digital System Fundamentals, 2020
Dale Patrick, Stephen Fardo, Vigyan ‘Vigs’ Chandra
Complex PLD (CPLD) devices contain several interlinked PAL devices and are equivalent to several thousand or more logic gates, all on one integrated circuit. CPLDs are configured to perform specific logic functions by programming these devices using an industry standard JEDEC (Joint Electron Device Engineering Council) file format. These files are generated by computer programs called logic compilers. The source code for the logic compiler is written using a HDL (Hardware Description Language) such as PALASM or ABEL (Advanced Boolean Expression Language).
Outdoor environmental sensitivity test for the detection of biological aerosols
Published in Instrumentation Science & Technology, 2021
Hyunsoo Seo, Kibong Choi, Jinho Park
The signal processing method involves four steps as shown in Figure S1. First, when particles are introduced through the nozzle, scattered light and fluorescence analog signals are acquired by the PMT. Next, for signal amplification, the analog optical signals are converted into voltages, which are supplied as inverting inputs, so that the phase of the output signal of the preamplifier is reversed. The amplification is repeated using an analog front-end amplifier (AD829, Analog Devices, USA). The amplified output voltage-of-fluctuation signals, VFT, are converted into digital signals by comparing them to the threshold voltage, VTHD. The digital signals are counted by varying the digital pulse width with respect to their intensities. Using a digital complex programmable logic device (CPLD; 5M2210ZF256I5N, Altera, USA), the pulse width signals are sampled at 1 MHz, and the device acts as an intermediate, so that, if the logical value is “1,” the signal is counted and sent to the microcontroller unit (MCU; STM32F420, STMicroelectronics, USA).
Source-side low-frequency harmonic suppression method for matrix converter
Published in International Journal of Electronics, 2021
By establishing a system model, the proposed strategy was simulated using Matlab/Simulink to verify the effectiveness of the method. The proposed MC control strategy was experimentally tested using a prototype. A platform was constructed using a digital signal processor (DSP) and a complex programmable logic device (CPLD). The bidirectional switch used in the experiment was obtained by connecting two insulated gate bipolar transistors (IGBT) and two diodes in anti-parallel as shown in Figure 10. In the experimental prototype, Hall voltage and Hall current sensors were used to sample input and output voltages and currents. Damping resistance Rd is connected in parallel with input filter inductance Lf to suppress input current resonance. Table 2 shows the system parameters under the proposed and conventional control strategies. Based on the setting of output asymmetry in Table 2 and (8), the maximum system voltage gain is as follows: . According to the setting of output asymmetry in Table 2 and equation (11), the theoretical values of the third harmonic contents in the input current are as follows: , .
DSP-FPGA based real time implementation of carrier based PWM technique for an indirect matrix converter
Published in Australian Journal of Electrical and Electronics Engineering, 2021
Payal Patel, Mahmadasraf A. Mulla
Owing to the highly complex control schemes, the hardware implementation of the MC topologies has remained a difficult task. The control of eighteen bidirectional switches with the four-step commutation is one of the major drawbacks of using the DMC topology. On the other hand, the use of two carriers to synchronise the two IMC stages renders the implementation process of the IMC topology a complicated task. Many real-time implementation methods for the MCs have been described in the literature for the DMC and IMC topologies (Muller, Ammann, and Rees 2005; Hamouda, Fnaiech, and Kamal 2007; Kolar et al. 2007; Jussila, Salo, and Tuusa 2003; Shao and Sun 2007; Dubey, Agarwal, and Vasantha 2007; Lopez et al. 2008; Bueno et al. 2008; Silva et al. 2010; Mukherjee et al. 2006; Sun et al. 2007; Hamouda et al. 2011; Khajeh et al. 2019). The authors Muller, Ammann, and Rees (2005) and Hamouda, Fnaiech, and Kamal (2007) have suggested the application of powerful DSP boards for implementing the MC control algorithms. However, these platforms are not fitted for industrial applications owing to their high cost. Kolar et al. (2007) and Jussila, Salo, and Tuusa (2003) investigated the use of a microcontroller in combination with the logic circuit. The above methods do not allow the use of the high switching frequency which decreases the power density of the MCs. Nowadays, in the various power electronic based applications, the use of DSP in combination with FPGA has become a common practice (Shao and Sun 2007; Dubey, Agarwal, and Vasantha 2007; Lopez et al. 2008; Bueno et al. 2008; Silva et al. 2010). Mukherjee et al. (2006) and Sun et al. (2007) explained that the DSP is used in conjunction with the complex programmable logic device (CPLD) to produce the switching patterns of the MCs. In the above approaches of the implementation, it is necessary to synchronise the timings of the various events in two devices. The new method of implementation using DSP-FPGA is presented by Hamouda et al. (2011), which does not need data transfer between these two devices. The microcontroller-based implementation of the space vector algorithm for IMC is presented by Khajeh et al. (2019).