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Nanotopography
Published in Ungyu Paik, Jea-Gun Park, Nanoparticle Engineering for Chemical-Mechanical Planarization, 2019
Semiconductor device fabrication on silicon wafers comprises steps at which layers are deposited, subsequently planarized, and structured. Planarization is typically performed using a polishing step where the smoothing of the layer is due to chemical interaction with the polishing slurry as well as mechanical abrasion. Therefore, such processes are called chemical-mechanical polishing (CMP) and they have been implemented, for example, in silicon wafer manufacturing for more than 30 years. The homogeneity of a post-CMP layer is limited by fluctuations of the combination of layer deposition and CMP, as well as the frontside topography of the substrate. These two contributions to post-CMP layer thickness deviations of oxide film need to be quantified properly for identifying potentials that allow improvement of the efficiency of planarization for future devices. This is particularly necessary since excessively large-layer thickness variations after CMP may have a negative impact on device performance such as leakage and the pinhole effect, and the thickness of layers might even decrease with the ongoing reduction of critical dimensions.
Connected Devices
Published in Saad Z. Asif, 5G Mobile Communications Concepts and Technologies, 2018
The microprocessors consist of billions of transistors which are glued together via a process called semiconductor device fabrication. The process technology (or technology node) is measured in nanometers (nm). For example, in the recent past, the 45 nm node referred to the smallest structure size of a single transistor, which is approximately 1,000 times thinner than the diameter of a human hair. Recently, for instance, Qualcomm's Snapdragon 820 mobile processor uses 14 nm low process technology. Thus, the advancements are ongoing to reduce the node size in order to achieve higher efficiencies.
Very-Large-Scale Integration Technology: History and Features
Published in A. Arockia Bazil Raj, FPGA-Based Embedded System Developer's Guide, 2018
In the early 1960s, the semiconductor manufacturing process was initiated in Texas, and in 1963, CMOS was patented by Frank Wanlass. ICs are manufactured by utilizing the semiconductor device fabrication process. These ICs are major components of every electronic device we use in our daily life. Many simple and complex electronic circuits are designed on a wafer made of semiconductor compounds, mostly silicon, by using different fabrication steps/processes. This technology is used in developing microprocessors, microcontrollers, digital logic circuits and many other ICs. It facilitates low power dissipation and high packing density with much less noise margin. The CMOS can be fabricated using different processes such as the N-well process, P-well process and twin tub process. The fabrication of a CMOS can be done by following 20 steps, through which the CMOS can be obtained by integrating both the nMOS and pMOS transistors on the same chip substrate. The integration of the nMOS and pMOS devices on a chip is done via a special region called a well or tub at which semiconductor type and substrate type are opposite each other. A P-well has to be created on a N-substrate and an N-well has to be created on a P-substrate. In this section, the fabrication of the CMOS is described using the P-substrate, in which the nMOS transistor is fabricated on a P-type substrate.
Influence of substrate temperature on coated engine piston head using multi-response optimisation techniques
Published in International Journal of Ambient Energy, 2022
S. Ganesan, S. Padmanabhan, J. Hemanandh, S. P. Venkatesan
Ceramic coating is a covering which is applied to the surface of an object, usually referred to as the substrate. The purpose of applying the coating may be decorative, functional, or both. It can be an all-over coating, completely covering the substrate, or it can only cover parts of the substrate. An example of coating is product label on many drink bottles on one side has an all-over functional coating (the adhesive) and the other side has one or more decorative coatings in an appropriate pattern (the printing) to form the words and images. Functional coatings may be applied to change the surface properties of the substrate, such as adhesion, wettability, corrosion resistance, or wear resistance. In other cases, e.g. semiconductor device fabrication (where the substrate is a wafer), the coating adds a completely new property such as a magnetic response or electrical conductivity and forms an essential part of the finished product.
Magnetohydrodynamic Effect on Thermal Transport by Silver Nanofluid Flow in Enclosure with Central and Lower Heat Sources
Published in Heat Transfer Engineering, 2022
Mahalakshmi Thangavelu, Nithyadevi Nagarajan, Ruey-Jen Yang
The effects of a magnetic field on the desired fluid flow and heat transfer performance within an enclosure have attracted significant interest due to many applications in the chemical industry (e.g., chemical vapor deposition on surfaces and crystal growth in liquids), power and cooling industry (e.g., cooling of nuclear reactors and electronic packages), petroleum industry (e.g., petroleum refining and petrochemicals) and semiconductor industry (e.g., semiconductor device fabrication and semiconductor fabrication plants). Also, it is well known that unavoidable hydrodynamic movements exist in the crystal growth. It is desirable to remove the unwanted flow in crystal growth to damp the convection flow. During operations, the undesirable amount of heat may be detrimental to the equipment, which is to be removed as fast as possible. Thus, use of an external magnetic field on natural convection has increasing application for better control and quality of the products. The influence of a magnetic field is applied in practical cases like crystal growth from the melt material manufacturing technology, cooling of nuclear reactor, petroleum industries, welding, casting, and hemodialysis.
A data-driven method for enhancing the image-based automatic inspection of IC wire bonding defects
Published in International Journal of Production Research, 2021
Junlong Chen, Zijun Zhang, Feng Wu
More complicated principles of developing features for the automatic vision inspection have been discussed (Chen and Perng 2016; Kuo et al. 2019). Chen and Perng (2016) utilised statistical textures extracted from images of the IC moulding surface to identify cracks, dilapidations, and voids. Yet, it required extra experimental efforts on obtaining identification thresholds which limited the practical value. Kuo et al. (2019) developed a number of judgment indicators based on defect types and set thresholds for identifying defects via indicators. The image-based quality inspection based on machine learning methods using different developed features has been discussed for LED and semiconductor products. Kuo et al. (2014) developed a two-step back-propagation neural network to classify surface and structural defects based on 5 external geometric features. Chang et al. (2007) introduced a learning vector quantisation neural network to identify defective dies in LED wafer images. Imoto et al. (2019) applied a convolutional neural network with transfer learning to classify defects in the semiconductor device fabrication. Specific advanced image-based frameworks for the IC wire bonding defect inspection need more explorations.