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Design of FINFET based DRAM cell for low power applications
Published in Arun Kumar Sinha, John Pradeep Darsy, Computer-Aided Developments: Electronics and Communication, 2019
Grande Naga Jyothi, Gorantla Anusha, N. Dilip Kumar, Debanjan Kundu
A DRAM memory cell is a capacitor that is charged to produce a ‘1’ or a ‘0’. The memory chip’s support circuitry allows the user to read the data stored in the memory’s cells, write to the memory cells, and refresh memory cells. This circuitry generally includes sense amplifiers to amplify the signal or charge detected on a memory cell. Address logic to select rows and columns. Row Address Select (RAS) and Column address Select (CAS) logic to latch and resolve row and column addresses and to initiate and terminate read and write operations. The block diagram of 1KB DRAM Architecture is shown in Figure 1. In order to get 1KB memory, 32 word lines are required. There are different type of decoder techniques one among them is NOR based decoder. In this DRAM cell design, NOR is based decoder used. This decoder requires less number of transistors and consumes low power compared to other techniques. Each block is specified in detail in further sections.
Force-System Resultants and Equilibrium
Published in Richard C. Dorf, The Engineering Handbook, 2018
The differences between a DRAM and SRAM stem fundamentally from different implementations of the memory cell. In an SRAM, the cell consists of a cross-coupled logic circuit built from four to six transistors; a SRAM memory cell will indefinitely remember the bit written to it as long as it is powered. In contrast, a DRAM cell is made from a single transistor and capacitor, and its memory is transient. The DRAM cell is written by charging its capacitor. This charge slowly leaks out of the device in the form of an electrical current so that without special intervention the information stored in the cell is irrevocably lost. As a consequence, DRAM cells need to be periodically refreshed every few milliseconds or so. To refresh a cell, its contents are read and then written back again, thereby replenishing the charge on the capacitor as needed. The need for refresh circuitry complicates the design and operation of the DRAM interface, and impacts its operating speed since some portion of the time is used by the chip for refresh. However, because of the small size of each cell, DRAM chips are much denser than SRAM and have four to six times the capacity. SRAM, by contrast, is much faster and consumes less power than the DRAM, but holds fewer bits per chip and is considerably more expensive than DRAM.
A-RAM Family Novel Capacitorless 1T-DRAM Cells for 22 nm Node and Beyond
Published in Santosh K. Kurinec, Krzysztof Iniewski, Nanoscale Semiconductor Memories, 2017
Francisco Gamiz, Noel Rodriguez, Sorin Cristoloveanu
The external storage element is a limitation for the DRAM survival. The step forward that each technology node requires in terms of technological, material, and design advances represents a paramount challenge for the integration of the capacitor inside the cells. This is the main reason of the increasing research activity during the last decade around new memory cells, free of capacitors. 1T-DRAM is a vast concept that includes a set of memories intended to be potential substitutes of the standard DRAM technology. All of them have a common feature: they avoid using any external storage element. The memory cell is composed of a single device (transistor or transistor-like) where the information is stored, that is, the same device is used to store the information and to read it. Within the 1T-DRAM family, a large collection of devices has been accommodated: from single transistors to more complicated multi-gate or thyristor-like structures [6]. In this chapter, we are going to focus on a particular set belonging to the 1T-DRAM family: the so-called floating-body (FB) 1T-DRAM cells.
Resistive Random Access Memory: A Review of Device Challenges
Published in IETE Technical Review, 2020
Varshita Gupta, Shagun Kapur, Sneh Saurabh, Anuj Grover
An SRAM cell stores information on the two nodes of a cross-coupled inverter pair. A DRAM cell uses a capacitor to store charge and distinguish between the “0” state and the “1” state. A Flash memory cell stores charge in the floating gate of a transistor and can store different amounts of charge to effectively store more than 1 bit of information per transistor [2]. This charge dependence of the storage mechanisms limit the scaling possibilities of present memory technologies. For example, the SRAM cell scaling is limited by the variability and the consequent impact on the functionality (read/write margins). The DRAM cell scaling is limited by the amount of charge that is stored on the scaled capacitor. The Flash memory scaling is limited due to the requirement of a high electric field in the program and the erase operations. Therefore, researchers are actively exploring non-charge-based memories that can be scaled to a greater extent [1,2].