China
Africa
Explore chapters and articles related to this topic
Dynamic Random Access Memory (DRAM)
Published in Shimeng Yu, Semiconductor Memory Devices and Circuits, 2022
DRAM relies on the charges that are stored on the SN capacitor for data storage. If there are sufficient charges on the SN capacitor, and the SN voltage is high (i.e., VDD), then it stores “1”; if there is no charge on the SN capacitor, and the SN voltage is low (i.e., ground), then it stores “0”. To write the data into the 1T1C bit cell is straightforward. “1” is written by biasing BL to VDD while turning on the WL with VPP, typically a higher voltage than VDD to facilitate the current passing through the cell transistor to charge the SN capacitor up to VDD. “0” is written by biasing BL to ground while turning on the WL with VPP, typically a higher voltage than VDD to facilitate the current passing through the cell transistor to discharge the SN capacitor down to the ground. During the hold operation, WL is turned off; thus, the charging state could maintain on the SN capacitor for some period of time. Due to the existence of leakage paths, the charging state will decay over time. Therefore, a periodic refresh is required for DRAM to maintain its memory state (which is different from SRAM). If the power supply is removed, the memory state is lost in DRAM. Therefore, DRAM is a volatile memory (same as SRAM).
Force-System Resultants and Equilibrium
Published in Richard C. Dorf, The Engineering Handbook, 2018
The differences between a DRAM and SRAM stem fundamentally from different implementations of the memory cell. In an SRAM, the cell consists of a cross-coupled logic circuit built from four to six transistors; a SRAM memory cell will indefinitely remember the bit written to it as long as it is powered. In contrast, a DRAM cell is made from a single transistor and capacitor, and its memory is transient. The DRAM cell is written by charging its capacitor. This charge slowly leaks out of the device in the form of an electrical current so that without special intervention the information stored in the cell is irrevocably lost. As a consequence, DRAM cells need to be periodically refreshed every few milliseconds or so. To refresh a cell, its contents are read and then written back again, thereby replenishing the charge on the capacitor as needed. The need for refresh circuitry complicates the design and operation of the DRAM interface, and impacts its operating speed since some portion of the time is used by the chip for refresh. However, because of the small size of each cell, DRAM chips are much denser than SRAM and have four to six times the capacity. SRAM, by contrast, is much faster and consumes less power than the DRAM, but holds fewer bits per chip and is considerably more expensive than DRAM.
Introduction to Semiconductor Memories
Published in Hai Li, Yiran Chen, Nonvolatile Memory Design, 2017
Data retention defines how long data can be properly kept in a memory cell. Similar to write endurance, data retention is mainly determined by the memory process technology. For instance, the data in a DRAM cell is represented as the voltage level on the capacitor. As the charge leaks away, the data becomes invalid after a period of time; for example, ~1 ms. Thus, periodical refreshing is required in DRAM to maintain the data. Data retention can be an issue even in nonvolatile memory. For example, the retention time of MRAM is significantly impacted by the temperature of the environment: when the temperature increases from 300 to 350 K, the retention time of the MTJ (cell for MRAM) decreases from 6,000 years to 4 years [16]. In commercial products, the data retention time of nonvolatile memory is usually more than 10 years at room temperature.
Ferroelectric, Piezoelectric Mechanism and Applications
Published in Journal of Asian Ceramic Societies, 2022
Arun Singh, Shagun Monga, Neeraj Sharma, K Sreenivas, Ram S. Katiyar
Therefore, The solid-state dynamics, random access memory (DRAM) is a one-transistor cell, which contains a sole capacitor storing the charge and a switching transistor to separate the capacitor. Ferroelectric materials have a high dielectric constant and high breakdown field, so they are used as a storage capacitor. Because of the large variation in the material characteristics, in crystal form it is necessary to employ the material whose temperature of transition is above the usual operating temperature of semiconductor chips, and for this particular application, ferroelectric materials in amorphous form are desirable. The amorphous ferroelectric materials do not show substantial variation in the dielectric constant with temperature and exhibit high breakdown field and high charge storage capacity, which makes them useful materials for DRAM [51–57].