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Published in Philip A. Laplante, Comprehensive Dictionary of Electrical Engineering, 2018
memory bounds register memory bounds register register used to ensure that references to memory fall within the space assigned to the process issuing the references; typically, one register holds a lower bound, another holds the corresponding upper bound, and accesses are restricted to the addresses delimited by the two. memory cell a part in a semiconductor memory holding one bit (a zero or a one) of information. A memory is typically organized as a twodimensional matrix of cells, with "word lines" running horizontally through the rows, and "bit lines" running vertically connecting all cells in that column together. See also bit line. memory compaction the shuffling of data in fragmented memory in order to obtain sufficiently large holes. See also memory fragmentation. memory cycle the sequence of states of a memory bus or a memory (sub-)system during a read or write. A memory cycle is usually uninterruptible. memory cycle time the time that must elapse between two successive memory operations. Usually larger than the memory access time. memory data register (MDR) a register inside the CPU that holds data being transferred to or from memory while the access is taking place. memory density the amount of storage per unit; specifically, the amount of storage per unit surface or per chip. memory element a bistable device or element that provides data storage for a logic 1 or a logic 0. memory fragmentation See internal fragmentation, external fragmentation. memory hierarchy See hierarchical memory. memory interleaving See interleaved memory.
Random Access Memories
Published in Muzaffer A. Siddiqi, Dynamic RAM, 2017
The last few decades have seen a tremendous increase in usage of semiconductor memories, and there has been no looking back. Digital circuits and systems are using semiconductor memories in ever-increasing proportion. Advances in technology and fabrication processes have resulted in a high rate of continuous increase in the memory density. Performance has also been improving, which has opened new application areas considered unreachable. A broad categorization of semiconductor memories is in terms of their ability to retain stored data when supply is stopped; volatile memories lose their data whereas nonvolatile memories retain it. Be it volatile or nonvolatile, in most of the semiconductor memories information can be stored or retrieved from any location, hence the term random access memories (RAMs). The basic arrangement of storage of data/information is done either in a bistable flip-flop called static RAM (SRAM) or through charging a capacitor in dynamic RAM (DRAM). Both SRAM and DRAM are volatile memories.
Solution-processed zirconium acetylacetonate charge-trap layer for multi-bit nonvolatile thin-film memory transistors
Published in Science and Technology of Advanced Materials, 2023
Song Lee, Jeong-In Lee, Chang-Hyun Kim, Jin-Hyuk Kwon, Jonghee Lee, Amos Amoako Boampong, Min-Hoi Kim
Nonvolatile memory devices such as flash memories with floating gates have received much attention due to the high demand on storage space and its possibility of NAND connection, multi-bit storage, and high memory density [1]. However, the charge-trap memory (CTM) transistor, similar to the floating-gate flash memory, rather uses an insulating layer with trap sites to trap and store charges instead of the conductor-based floating gate for high memory retention [2]. The CTM is characterized by many advantages compared with other nonvolatile memories including non-destructive writing/reading, feasibility of being integrated with traditional complementary metal-oxide semiconductor technique, single device identification in a complex circuitry and finally the implementation of NAND flash memory [3]. Programming and erasing processes of the CTMs are performed by trapping and de-trapping charges respectively within the charge storage insulating layer. Silicon nitride (Si3N4) has been extensively used as a charge storage layer for most commercialized CTM products [4]. However, there is a high possibility of charge leakage due to the small conduction band barrier at the Si3N4/SiO2 interface. Therefore, extensive research is currently being conducted on high-k dielectrics such as the metal oxides (Ta2O5 [1], TiO2 [5], HfO2 [6], ZrO2 [7]) as charge trap layers, because of the higher conduction band barrier at the interface with SiO2 compared to the Si3N4 for better charge retention.