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An Overview of Current Trends in Hafnium Oxide–Based Resistive Memory Devices
Published in Shilpi Birla, Neha Singh, Neeraj Kumar Shukla, Nanotechnology, 2022
Lalit Kumar Lata, Praveen Kumar Jain, Abhinandan Jain, Deepak Bhatia
RAM was initially used for random access memory but is now used to designate read/write memory. It may be volatile or nonvolatile. In volatile memory, all the data are destroyed when the power supply is removed, whereas in nonvolatile memory, there is no loss of data, even if the power supply is switched off. RAM has two types: SRAM (static RAM) and DRAM (dynamic RAM). These memory devices have their benefits and drawbacks. For example, the capacity and density of DRAM are high, but this memory is volatile, and power consumption is high because it needs to be refreshed every second. SRAM is fast but volatile, and large memory cells reduce its capacity. Compared to RAM, flash memory is incredibly well-liked, features a very high capacity, and is nonvolatile; however, it is relatively slow. Since no existing memory meets all criteria, development is needed to continuously search for new technologies. The perfect memory should have high capability, provide a speedy response, have long retention time, use low power consumption, be nonvolatile and have higher scaling than existing technology [1–5].
Advanced Digital Concepts
Published in Dale Patrick, Stephen Fardo, Vigyan ‘Vigs’ Chandra, Electronic Digital System Fundamentals, 2020
Dale Patrick, Stephen Fardo, Vigyan ‘Vigs’ Chandra
RAM is form of volatile memory, which means that these devices lose any stored data if power to the IC is removed. They thus need to be constantly powered to ensure data storage. The primary use of RAM is to temporarily store microprocessor based program instructions and the data needed by the programs. For example, information regarding the cursor or mouse on the screen needs to be updated constantly while a computer is on, as also information about any programs which are running.
Microcontroller Hardware
Published in Syed R. Rizvi, Microcontroller Programming, 2016
RAM stands for Random Access Memory and is often referred to as read/write memory. The RAM is a general-purpose volatile type of memory, where the information (data or programs) is lost after the power is switched off. By default, the HC11E9 RAM is located at $0000–$01FF of the memory map. To achieve the flexibility with on-chip and off-chip resources, the user is given the ability to relocate the RAM in the memory map by altering the RAM map position control bits in the INIT register. Figure 3.19 shows the structure of the 8-bit INIT register where the four bits, such as RAM3, RAM2, RAM1, and RAM0 specify the most significant hex digit of the 16-bit RAM address in the memory map. As shown in Table 3.7, the location of RAM can be moved to the start of any 4K memory block. Recall that the HC11 uses a 16-bit address. Therefore, since 4 bits are already used, only 12 bits of the 16-bit address remain to be used. The maximum number of memory locations that can be addressed with the remaining 12 bit is 212 = 4K. Before we move on to the next type of memory in HC11, let us take an example to see how the RAM mapping can be changed using the INIT register.
Design of four-state DRAM using novel MOSFETs
Published in International Journal of Electronics Letters, 2018
A dynamic random-access memory (DRAM) needs a transistor and a capacitor for every bit of data, whereas static random-access memory (SRAM) needs six transistors. Because of that, DRAM module has more capacity than SRAM module. Integration at the higher technology node is facing different challenges in the current semiconductor world (Huang et al., 2009; Zaitseva & Levashenko, 2013). The integration can be increased further by storing multiple bits per DRAM circuits. To design multivalued DRAM cell, proper semiconductor devices are necessary. The possibility for different semiconductor devices to implement multivalued logic is in research phase (Deng and Wong, 2007; Chen et al., 2013; Emani et al., 2012; Figueiredo et al., 2008; Jimmy & Narkhede, 2015; Karmakar, 2016, 2014a; Karmakar, Chandy, & Jain, 2011; Karmakar, Gogna, & Jain, 2016; Karmakar, Gogna, Suarez, & Jain, 2015; Karmakar & Jain, 2015a, 2015b; Karmakar, Suarez, Gogna, & Jain, 2012; Karmakar, Suresh, Chandy, & Jain, 2009; Lin, Kim, & Lombardi, 2011; Liu, Lee, & Guo, 1991; Schwierz, 2010; Seabaugh et al., 1989; Slight et al., 2008; Son et al., 2006; Stock et al., 2001). Four states can be generated by modifying the channel region or the gate region of the metal oxide semiconductor field-effect transistor (MOSFET). In spatial wave-function-switched FETs (SWSFETs) (Karmakar, 2013a; Karmakar, Chandy, & Jain, 2015a, 2012; Karmakar et al., 2015a; Karmakar, Chandy, & Jain, 2015b; Karmakar & Jain, 2016; Karmakar, Jain, Chandy, & Heller, 2012), four states are generated because of switching of charge carriers between different channels. On the other hand, QDG-QDCFET (Jain et al., 2012; Karmakar, 2014b, 2013b) also generates four states because of mutual effect of quantum dots in the gate region and channel region of the FET. This paper discusses the design of four-state DRAM cell using QDG-QDCFET and SWSFET. The device structure and operation are discussed in Section 2 which is followed by fabrication in Section 3. Section 4 introduces circuit model. Quaternary DRAM and its physical layout are discussed in Sections 5 and 6 which are followed by conclusions in Section 7.