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Dynamic Random Access Memory (DRAM)
Published in Shimeng Yu, Semiconductor Memory Devices and Circuits, 2022
DRAM chips have specially designed input/output (I/O) interfaces following a certain protocol. One of the most widely used interfaces is the double-data-rate (DDR) series, which is a synchronous mechanism to boost the data transfer rate given a limited DRAM internal clock frequency. For example, the DRAM internal clock cycle time is 5 ns (thus the frequency is 200 MHz) due to the required time for correct sensing. The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal), and thus is referred to as the double data rate. DDR effectively doubles the I/O bandwidth at the same internal clock frequency, achieving 400 M bit per second per I/O pin (i.e., 400 Mbps/pin), and thus 3.2 GB/s for a 64-bit-wide DIMM. Since its invention, the DDR protocol has extended to several generations. For example, DDR2, DDR3, DDR4, and DDR5 simply means the interface clock frequency will be running at a 2×, 4×, 8×, and 16× higher frequency than the DRAM internal clock frequency, resulting in substantial boosts of the I/O bandwidth. Take an example of the DDR3; if the DRAM internal clock frequency is 200 MHz, and the interface clock frequency is 800 MHz, it results in 1600 Mbps/pin, and thus 12.8 GB/s for a 64-bit-wide DIMM.
Force-System Resultants and Equilibrium
Published in Richard C. Dorf, The Engineering Handbook, 2018
SDRAM, the current-volume industry-standard DRAM has several advantages over FPM/EDO. First SDRAM operates synchronously with the system clock increasing performance, and provides flexible programmable block access modes to control burst length and column access order. In addition, the internal architecture of SDRAM supports a multiple bank organization. The separate banks can be controlled so that while one bank is being read, another can be primed by activating its RAS, an operation known as precharging. Consequently, different rows can also be accessed in burst mode as long as they reside in different banks, resulting in high memory bandwidth. DDR SDRAM is similar to SDRAM, but doubles the memory bandwidth by transferring data twice per clock cycle, at both the rising and falling edges of the clock.
Case Studies
Published in Lambrechts Wynand, Sinha Saurabh, Abdallah Jassem, Prinsloo Jaco, Extending Moore’s Law through Advanced Semiconductor Design and Processing Techniques, 2018
Lambrechts Wynand, Sinha Saurabh
Its latest offering, announced in 2017 and planned to be mass-produced in 2018, is the Volta line of GPUs, a processing unit based on a 12 nm FinFET technology node, housing 21 billion transistors in its main processing core on a die size of 815 mm2 (Nvidia 2017). Its predecessor, the Pascal line of GPUs, was built on a 14 nm technology and contained 15 billion transistors on a die size of 610 mm2 on its primary processing core. Huang additionally said, during this keynote address, that the Volta GPU is at the limits of photolithography, therefore acknowledging that this process step (photolithography) is the primary challenge to adhering to Moore’s law. The Volta line of GPUs has a redesigned microprocessor architecture with respect to the Pascal line, and is able to operate 50% more efficiently than its predecessor. In addition, these GPUs implement high bandwidth memory (HBM) for their video RAM (VRAM), as opposed to the traditional, albeit less costly, double data rate (DDR) memory – currently type 5, GDDR5 (Nvidia 2017). HBM uses vertically stacked dynamic RAM (DRAM) memory chips interconnected by through-silicon vias, shortening the path between individual memory chips, effectively reducing power consumption, reducing the required area and allowing for higher bandwidth at lower clock speeds.
A comparative study between PCR, PLSR, and LW-PLS on the predictive performance at different data splitting ratios
Published in Chemical Engineering Communications, 2022
The simulations for this work were operated using the computer configuration specifications such that Central processing unit model: Intel Core i5-4210U operating at a base frequency of 1.70 Ghz (2 cores 4 threads), Random-access memory: 12 Gigabytes Double Data Rate 3L Cycles 11 (small outline dual in-line memory module), Operating System: Windows 8.1 64-bit, and MATLAB version R2019b. All simulations were done on the same system to affirm the consistency of the results.