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Printed Wiring Boards
Published in Jerry C. Whitaker, Electronic Systems Maintenance Handbook, 2017
Ravindranath Kollipara, Vijai Tripathi
The term signal-integrity refers to the issues of timing and quality of the signal. The timing analysis is performed to ensure that the signal arrives at the destination within the specified time window. In addition, the signal shape should be such that it causes correct switching and avoids false switching or multicrossing of the threshold. The board features that influence the signal-integrity issues of timing and quality of signal are stub length, parallelism, vias, bends, planes, and termination impedances. Increasing clock speeds and signal edge rates make the signal-integrity analysis a must for the design of high speed PWBs. The signal-integrity tools detect and help correct problems associated with timing, crosstalk, ground bounce, dispersion, resonance, ringing, clock skew, and susceptibility [Maliniak 1995]. Some CAD tool vendors offer stand-alone tools that interface with simulation and layout tools. Other vendors integrate signal-integrity capabilities into the PWB design flow. Both prelayout and postlayout tools are available. Prelayout tools incorporate signal-integrity design rules up front and are used before physical design to investigate tradeoffs. Postlayout tools are used after board layout and provide a more in-depth analysis of the board. A list of commercially available signal-integrity tools is given in Maliniak [1995] and Beckert [1993]. A new automated approach for generating wiring rules of high-speed PWBs based on a priori simulation-based characterization of the interconnect circuit configurations has also been developed [Simovich et al. 1994].
Continuous-Time Circuits
Published in Tertulien Ndjountche, CMOS Analog Integrated Circuits, 2017
Due to factors such as the fabrication tolerance, temperature variation and aging, the values of components can drift to about 10% to 50% from their nominal specifications. The automatic tuning scheme included in CT filters provides a means to solve this problem. When the requirement of a high dynamic range results in a large power consumption and the noise level can be reduced only at the price of a large chip, it is common to adopt a solution based on multiple integrated circuits (ICs) and discrete components instead of a monolithic IC. With the down-scaling of MOS transistors into the submicrometer regime, analog and digital circuits may share the same die on a single chip in mixed-signal design. The result is the onset of several problems related to the signal integrity, substrate noise, crosstalk, interconnect parasitic impedances, and electromagnetic interference. By increasing the dynamic range, differential architectures can reduce the sensitivity to some of these effects and supply voltage variations.
Signal Integrity and Reliability of Network-on-Chip
Published in Santanu Kundu, Santanu Chattopadhyay, Network-on-Chip, 2018
Santanu Kundu, Santanu Chattopadhyay
Another major cause of signal integrity is the IR drop effect caused by wire resistance and current drawn from the power and ground grids. If the wire resistance is too large or the cell current is higher than predicted, an undesirable voltage drop may happen. The voltage drop causes the voltage supplied to the affected cells to be lower than required, which leads to larger gate and signal delays, which in turn can cause timing fault in the signal paths as well as clock skew. Voltage drop on power and ground grids can also affect the noise margins and compromises the signal integrity of the design. Therefore, special attention should be taken to resolve the IR drop effects during post-layout phase.
Signal integrity analysis on a microstrip ultra-wideband coupled-line coupler
Published in International Journal of Electronics, 2019
Saffrine Kingsly, Sangeetha Velan, Malathi Kanagasabai, Sangeetha Subbaraj, Yogeshwari Panneer Selvam, Bhuvaneswari Balasubramaniyan
The aim of signal integrity analysis is to affirm acceptable high-speed data transmission. These signal integrity issues occur due to impedance discontinuities, transmission line effects and improper power distribution. In this section, the signal integrity analysis of the proposed coupled-line coupler is presented at 3.5 GHz and 5 GHz which has been considered as the sampling frequency in the UWB frequency range. The analysis is executed using two modulation schemes BPSK and QPSK which are the basic and the most prevalent modulation schemes used in most of the modern communication systems. The analysis was done at 25 MSPS (Million Samples Per Second) data rate with 40 MHz span using Agilent E4438C ESG vector signal generator and Agilent MXAN 9020A signal analyser.