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Sequential Circuits
Published in Wen-Long Chin, Principles of Verilog Digital Design, 2022
The shift control input (shift_en) determines when and how many times the register A are loaded or shifted. This is done with an AND gate that allows clock pulses to pass into the clock terminals of registers only when the shift control signal is high. Gating the clock signal is called clock gating. This practice may be problematic because it may influence the clock path of the circuit so that glitches may be produced on the tx_clk_gated signal. The functionality of the shift register can fail owing to extra edges on the tx_clk_gated signal. Therefore, the control signal, shift_en, should be carefully designed so that no glitch can be produced in the gated clock.
Clock signal and its attribute for agriculture
Published in Govind Singh Patel, Amrita Rai, Nripendra Narayan Das, R. P. Singh, Smart Agriculture, 2021
A clock signal is the reference signal used to compare as a reference in circuits for synchronization of input and output signals. The clock signal has a definite period, and half of the period is known as pulse width which changes its value from high to low or low to high (Jovanović et al. 2003). Clock signals are used as the reference or pulse signals in most of the electronic systems today. Many of us generally regard the clock signals as only control signals. However, the following attributes make the clock signals significant (Earl McCune 1994): They possess the greatest fan-out.They travel enormous distances in any circuit.They typically operate at the highest speed possessed in the circuit concerning both control and data signals.
A Cost-Effective TAF-DPS Syntonization Scheme of Improving Clock Frequency Accuracy and Long-Term Frequency Stability for Universal Applications
Published in Fei Yuan, Krzysztof Iniewski, Low-Power Circuits for Emerging Applications in Communications, Computing, and Sensing, 2018
Liming Xiu, Pao-Lung Chen, Yong Han
Frequency links time through the clock. Time is produced by a clock signal and is used to coordinate events inside an electronic system. In a network structure, timing is always passed from clocks of a given stratum performance level to clocks of a lower or equal stratum performance level [4–9]. Clock signal can be directly generated from a frequency source, or indirectly through a phase-locked loop (PLL). Frequency source is found in military, metrology, industrial, consumer, communication network, automotive, power grid, banking, and scientific research electronic systems. In all those systems, frequency stability influences the system performance from multiple directions: the slip rate in digital communication (such as STN, NTP, and PTP) [6,8], the precision in navigation systems (such as GPS) [9,10], the time accuracy in bookkeeping (such as in power grids, banking, and stock trading) [11, 12], and the improvement in military warfare (e.g., improved spectrum utilization, higher jamming resistance, fast signal acquisition, longer life, and smaller size, weight, or cost) [13], among others. In addition, with the adoption of atomic standards and the complexity of today’s sophisticated applications, modern systems also need to consider the impact of relativity on the accuracy of the clock [14,15].
On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies
Published in International Journal of Electronics, 2022
Pritam Bhattacharjee, Gaurav Trivedi, Alak Majumder
As per the present discussion, instantaneous current is a parameter influenced by the rigorous participation of clock in the on-chip sequential operations. The clock signal is generated using an off-chip crystal oscillator and is distributed through clock distribution network (CDN) to each of the relevant components inside the chip. It is noted that both CDN as well as the on-chip components are connected to the on-chip and rails. While the clock signal activity is exorbitant during the clock distribution, pumping of from is quite high due to dynamic increase of current requirement inside the chip as the sequential circuit operations are in execution (Vittal & Marek-Sadowska, 1997). When the clock is switching from logic ‘0’ to ‘1’ or vice-versa, most of the circuital nodes of this clock-dependent sequential circuit change their voltage levels instigating the excess flow of and result in more drawing of current from .
Variation aware design of controlled voltage swing ring oscillator
Published in International Journal of Electronics, 2020
Abir J. Mondal, J. Talukdar, Bidyut K. Bhattacharyya
The design of a stable ring oscillator is an essential part for any chip designer to generate a high frequency clock inside the chip. Normally a frequency greater than 800 MHz is the maximum available crystal frequency which can be mounted into printed circuit board (PCB) board in order to connect with chip. This also feeds into the phase lock loop (PLL) circuit and a stable ring oscillator works as a VCO for that purpose. Similar design is essentially required for any high speed communication system, but there appears lot many challenges (Mezzavilla, Zanella, Rangan, & Rappaport, 2017). Some of these challenges are minimising cost and decreasing power consumption while maintaining the speed. All such performance parameters are related to the timing scheme of a system. Thus the modern communication systems, require a stable periodic signal (also called the clock signal) to provide the timing basis for sampling, frequency synthesis, etc. (Bhowmik, Pradhan, & Bhattacharyya, 2017; Lee & Abshire, 2016). Generation of periodic clock signal is the main bottleneck in high speed communication systems. With increasing data speed, the clock period becomes shorter decreasing the amount of absolute timing uncertainity that can be tolerated at the output (Wary & Mandal, 2015). The periodic signal of a clock generator is generated from a ring oscillator. Accordingly, the periodic signal is buffered before driving other circuitry that requires the timing information.
Resource allocation in rooted trees for VLSI applications
Published in Optimization, 2019
Another type of VLSI design optimization problems regards the distribution of the clock signal over the chip as in the seminal work [7] and in [8]. Such problems are solved as a part of the clock-tree synthesis (CTS), an essential part of chip design flow. CTS is attracting lately high attention and extensive study due to the very aggressive design constraints imposed on the clock signal distribution in the era of nanometer-scale VLSI silicon technologies. A well-known technique to meet such constraints is to skew the clock signal by inserting delay buffers (weights) into the clock tree’s nodes. The authors of [20,21] considered such problem for chips operated in multiple voltages. They claimed for optimal solution (by experiments and simulations) with the objective of minimizing the number of adjustable delay buffers, with delays bounded in some range. Their algorithm, however, is inefficient since it is based on solving set-covering problem, which is intractable and not scalable to industrial-size problems. It can be however be transformed similarly to inverse 1-median problem.