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Towards Multicores: Technology and Software Complexity
Published in Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi, Design of Cost-Efficient Interconnect Processing Units, 2020
Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi
System correctness and robustness are based on the clock period, since signals must obey certain inequalities (margins) in respect to timing. The clock cannot be distributed at the same instant to all on-chip components, because of the clock skew, defined as the maximum difference in clock arrival times (positive or negative phase shift) in any two periods, i.e. the clock signal in a synchronous circuit arrives at different components at different times. Clock skew is caused by unavoidable variations in buffer load, interconnect wire lengths, manufacturing process spread across die changing resistance, inductance, capacitance values, or temperature gradients. While performance of digital circuits is generally more immune to mismatch than analog circuits, synchronous design is sensitive to skew variations in the clock distribution network. Clock skew contribution to clock cycle time can be reduced by minimizing total wire length using an H-tree (or other possibly hybrid structures) with non-uniformly placed intermediate dummy buffers. Jitter slightly changes the clock period due to variations in Phased Lock Loop (PLL) oscillation frequency and noise sources. Jitter can be reduced by minimizing power supply noise (IR and Ldi/dt). Moreover, jitter due to PLL noise also improves with CMOS scaling.
Digital Systems
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
Festus Gail Gray, Wayne D. Grover, Josephine C. Chang, Bing J. Sheu, Roland Priemer, Rung Yao, Flavio Lorenzelli
Clock “skew” is defined, most generally, as the difference in time between the actual and the desired instant of active clock edge at a given clocked storage element. In the majority of designs in which the desired instant of clocking is the same at all storage elements, skew is the maximum difference in clock waveform timing at different latches. Clock skew is of concern because it ultimately leads to the violation of setup or hold times within latches, or to clock race problems in multiphase clocking. Furthermore, from a design viewpoint, uncertainty in clock timings must be treated as equivalent to actual clock skew. Skew or timing uncertainty are therefore equivalent to an increase in critical path logic delay. In either case, the clock period must be extended to ensure valid logic levels and proper setup/hold requirements relative to the clock time.
Integrated Circuits
Published in Jerry C. Whitaker, Microelectronics, 2018
As discussed earlier, clock skew is mainly caused by the imbalance of the clock distribution network. Such an imbalance can be the result of distance differences from the nearest clock driver, different functional blocks driven by different clock drivers with different driving strengths, temperature difference on the same die, device characteristic differences on the same die due to process variation, etc. Two general approaches are often taken to minimize the clock skew. The first approach deals with the way the clock signal is distributed. The geometric shape of the clock distribution network is a very important attribute. Depending on the type of system operation, several popular distribution network topologies are illustrated in Fig. 5.4. Among these topologies, H-tree presents least amount of clock skew and, therefore, is widely used in high-performance systems.
Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications
Published in Australian Journal of Electrical and Electronics Engineering, 2018
R. A. Walunj, S. D. Pable, G. K. Kharate
The spatial variation in arrival time of clock transition at different clocked elements is referred to as clock skew. The delay taken by clock signal to move through CDN to the clocked elements is called as latency. Variation in latency can be termed as skew. For H-tree un-buffered network, latency can be given as (Zarkesh-Ha, Mule, and Meindl 1999)