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Sequential logic elements
Published in J. R. Gibson, Electronic Logic Circuits, 2013
Sequential logic systems are usually divided into two groups, synchronous and asynchronous circuits. A synchronous circuit or system is one in which all the changes take place simultaneously at a time determined by a signal at some control input common to all sections. In an asynchronous system there is no common control; a change in one section of the system causes further changes in other sections and so on. The changes propagate through the system in a manner which is determined only by the speed with which each section operates.
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Published in Philip A. Laplante, Comprehensive Dictionary of Electrical Engineering, 2018
synchronized CDMA example carrier frequency offset, carrier phase, or symbol timing. synchronized CDMA a CDMA system where all the users are time-synchronized, i.e., the signals associated with all users arrive at the receiver with identical time delays. synchronizing coefficient electrical torque component in phase with the rotor angle. synchronizing relay a relay that monitors the voltage across an open circuit breaker to determine the frequency and phase relationship of the voltage sources on either side of the breaker. Synchronizing relays are used on generator breakers to bring the generator to the system frequency and to match the phase angle between the generator and system prior to closing the breaker. synchronous an operation or operations that are controlled or synchronized by a clocking signal. synchronous bus a bus in which bus transactions are controlled by a common clock signal and a fixed number of clock periods is allocated for specific bus transactions. Compare with asynchronous bus. synchronous circuit a sequential logic circuit that is synchronized with a system clock. synchronous condenser an unloaded, overexcited synchronous motor that is used to generate reactive power. synchronous demodulation a form of a phase sensitive angle demodulation in which local oscillator is synchronized or locked in frequency and phase to the incoming carrier signal. synchronous detection demodulation scheme using a balanced modulator to translate the center frequency of an IF signal down to DC (i.e., zero Hz). A local oscillator (LO) tuned to the IF center frequency is injected into one of the input ports of the balanced detector, while the AM or SSB signal containing the information is applied to the other. When used in this manner, the LO is often referred to as a beat frequency oscillator (BFO). Low-pass filtering the output results in retrieval of the intelligence signal, superimposed upon a DC voltage (or current, dependent upon the actual device). The DC value may either be discarded via high-pass filtering, or used as a received signal strength indicator for use in automatic gain control circuits. synchronous digital hierarchy (SDH) an international interface specification for high-speed optical fiber transmission networks that allows different manufacturers' equipment to be interconnected with full maintenance and signal transparency. Specifies the optical parameters and the basic rates and formats of the signal. Emphasizes protection from faults and fast restoration of service after service interrupts. synchronous drive a magnetic drive characterized by synchronous transmission of torque, typically using a salient pole structure. There is no slip between the driver and the follower. synchronous machine an AC electrical machine that is capable of delivering torque only at one specific speed (n s ), which is determined by the frequency of the AC system ( f ) and the number of poles (P) in the machine. The relationship between synchronous speed and the other variables is n s = 120 f /P synchronous motor an AC motor in which the average speed of normal operation is exactly proportional to the frequency to which it is connected. A synchronous motor generally has rotating field poles that are excited by DC. synchronous operation an operation that is synchronized to a clocking signal.
Multi-energy harvesting SIMO converter with energy prediction and adaptive output priority
Published in International Journal of Electronics, 2018
Chuang Wang, Zunchao Li, Lijuan Zhao
where , and mean whether , and is hungry, presents whether considers the priority of the storage output. Noting that, when , , , or is ‘1’, the corresponding parameter means ‘yes’. Because asynchronous circuit has the advantages of requiring less standard cells, needing no clock module and consuming less power compared against synchronous circuit, and these advantages favour the low power target of the proposed SIMO boost converter harvesting the limited energy. Thus, according to the aforesaid Karnaugh Map, the general schematic of adaptive output priority can be achieved via using asynchronous D flip flops as shown in Figure 5a. However, in our case the intermediate control signals can be reduced according to the followings: Because the storage output is a spare source requiring no constant voltage and discharges less often than the other two, it is set as the lowest priority. That is, .When the outputs and are simultaneously hungry, has the higher priority. This is because the converter would fail if as the supply of the converter is not high enough. Thus, .