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Nanoscale CMOS Memory-Based Security Primitive Design
Published in Mark Tehranipoor, Domenic Forte, Garrett S. Rose, Swarup Bhunia, Security Opportunities in Nano Devices and Emerging Technologies, 2017
The SRAM cells in a memory are arranged in a matrix of rows and columns. Cells in the same column share common bitlines and hence only one cell per column is accessed at any time. A cell is written by setting one bitline high and the other low and then asserting the wordline to transfer the bitline values to the cell. In an SRAM read operation, both bitlines are first charged and equalized by the column's precharge circuit. Next, the wordline for the desired row is asserted to connect the cell to the precharged bitlines. Depending on the stored value in the cell, transistor n1 or n2 will begin to discharge one of the bitlines through the corresponding access transistor. The discharge rate of the bitline varies depending on the random variation of the transistors that are discharging it, but these variations are masked because the time allowed for bitline discharge is conservative. After discharge, the column's sense amplifier is activated to detect the difference in voltage across the two bitlines and generate from it a digital 0 or 1 value that can be read out from the SRAM.
Memory Devices
Published in Chinmay K. Maiti, Introducing Technology Computer-Aided Design (TCAD), 2017
In this chapter, we discuss the key challenges in designing Flash memories. Scaling the tunnel oxide thickness in nonvolatile memories (NVMs) is examined. Semiconductor memory can be divided into two categories, volatile memory and NVM. In volatile memory, the information is saved only as long as the system power is on. SRAM and the DRAM fall into this category. A typical SRAM cell is composed of six transistors and is commonly used in the cache memory of a central processing unit due to its very high switching speed between two states. It is capable of writing and reading a bit in just a few nanoseconds. However, its drawback is its big size, which results in a low density such that it is not feasible for a high-density memory array. Unlike the 6T-SRAM cell, the DRAM cell typically consists of only one transistor and one capacitor (1T–1C). The DRAM is mainly used in the main memory due to its small cell size. It can be built with a high density, which enables overall high-speed data access to recently used data. The drawback of DRAM is that the capacitor for each cell is leaky, and the cell needs to be refreshed periodically to avoid loss of the stored data. Scaling issues are related directly to the need to store a critical amount of charge on the capacitor over time.
Introduction to microcontrollers and this book
Published in Ying Bai, Microcontroller Engineering with MSP432, 2016
The memory spaces also can be divided into the catch and heap areas based on the materials used to build the memory, and the former is made of high-speed static RAM (SRAM) and the latter is made of dynamic RAM (DRAM) with relatively slower accessing speeds. The advantage of using the SRAM is that a higher memory accessing speed can be obtained, but much more MOSFETs are utilized for each SRAM unit and therefore makes the memory structure complicated with higher cost. The advantage of using DRAM is that higher memory densities or integration intensities can be obtained with much simpler MOSFET structure and lower cost for each DRAM unit, but the working speed is relatively slower because of an additional refresh circuit applied on the DRAM. Because of the cost issue, the size of SRAM or the catch memory is regularly small but the size of the heap or DRAM is huge.
Comparative Analysis of Delay-Based and Memory-Based Physical Unclonable Functions
Published in IETE Technical Review, 2022
Priti S. Lokhande, Sangeeta Nakhate
The Static Random-Access Memory (SRAM) PUF was first introduced by Holcomb [17,18] and simultaneously by Jorge Guajardo [19]. In SRAM PUF the start-up state introduces randomness in the circuit. SRAM cells are made up of six transistors. The structure of the SRAM cell is shown in Figure 5. A single-bit can be stored in each SRAM cell. SRAM PUF’s operation is based on bistable elements. It is impossible to change a stable state after it has been chosen unless it is externally altered. In the switched-off state of the SRAM cell, Q and Q− values are 0, in the switched-on state, they are either 01 or 10 and when they are 11, the condition is unstable and unreachable. When the SRAM cell is switched on, which stable state will be chosen by the circuit depends upon the production process variation of its component. This stable state is unpredictable and can be used for randomness. SRAM PUF has an Inter-HD of 49.97% and an Intra-HD of 3.57%, according to experimental results [19] .
Process Corners Analysis of Data Retention Voltage (DRV) for 6T, 8T, and 10T SRAM Cells at 45 nm
Published in IETE Journal of Research, 2019
Ultra low power and high stability are the hunt areas in semiconductor technology nowadays. Continuous device scaling in advanced technology demands enhanced performance. The subthreshold operation results in low power, however, with reduced reliability. As scaling progresses, process variation becomes severe to handle. Static random access memory (SRAM) is the main memory block used in today's high performance processor due to its compatibility with the logic. In fact, the largest area in modern system on chip (SoC) is occupied with SRAM. The design of low power SRAM is in itself a big challenge to deal with. Further scaling and process variations are big obstacles to low power SRAM design [1,2]. SRAM is mainly used for storing and retrieving data. Data preservation without corruption is required at low voltage. The minimum supply voltage for which the data can be preserved in the SRAM is known as the DRV i.e. Data retention voltage. The stability of the SRAM cell [3] and hence the DRV of the cell are affected by the process variations. The process corner analysis is used for the analysis of process variations. It is believed that if the circuit performs well at each process corner, the circuit design is good enough [4] but if is not performing well, then the design needs reconsideration.
The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology
Published in Radiation Effects and Defects in Solids, 2018
N. S. Yusop, A. N. Nordin, M. Azim Khairi, N. F. Hasbullah
Static random access memory (SRAMs) cells are high-speed semiconductor memory that use flip-flop to store each bit. The circuit is said to be static as the stored data can be retained indefinitely if power is being supplied. Basic SRAM (Figure 1) consists of two PMOS and four NMOS transistors that build up a single memory cell, where each bit is stored. Millions of cells make an array of memory (1).