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Digital Logic Circuit Families
Published in Nassir H. Sabah, Electronics, 2017
The designation “digital logic circuit family” refers to digital ICs that are manufactured using the same technology and have the same circuit structure, such as the CMOS logic family. The circuits of a given logic family share common features that are characteristic of the given family, including the voltage levels that represent logic 1 and logic 0, noise immunity, propagation delay, rise and fall times of pulse signals, power dissipation, operating temperature range, availability of complex functions, and cost. The circuit modules of the same family can be readily connected together, but interconnecting modules from different families require special interface circuits because of differences in the voltages representing logic 1 and logic 0. The basic features of the important logic families at present are considered in this chapter.
Digital Electronics
Published in Trevor Linsley, Electronic Servicing and Repairs, 2014
The simplicity of digital electronics with its straightforward on off switching means that many logic elements can be packed together in a single integratedcircuit and packaged as a standard dual-in-line IC as shown inFigs. 4.19 and21. Different types of semiconductor circuitry can be used to construct the logic gates. Each type is called a logic family because all members of that integrated circuit family will happily work together in a circuit.
Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS Technology
Published in IETE Journal of Research, 2023
Domino logic is a clocked logic family which means that there is a clock in every logic gate. The continuous switching of clock in domino logic design leads to the higher power dissipation [4]. There are various domino logic topologies with modification in the keeper circuit to tolerate the device process parameters [5]. A variable strength keeper technique in [6] was design to chieve robust, high-speed, and low-leakage dynamic logic gates with carbon nanotube transistors. Low leakage domino logic is also design in [7] using carbon nanotube field effect transistor (CNTFET). Previous domino logic techniques maintain clock at high state during standby mode in order to reduce the static power dissipation. Here, we will propose a domino logic using clock gating technique and revised keeper circuitry using 16 nm CMOS technology. blueThis work have been inspired from the work done in [8]. In [8], a modified keeper consisting of both PMOS and NMOS transistors are used to reduce the power consumption of CMOS domino logic. This work uses the keeper which consists of only PMOS transistors with clock gating technique.
Quantum-dot Cellular Automata Latches for Reversible Logic Using Wave Clocking Scheme
Published in IETE Journal of Research, 2023
Debajyoty Banik, Hafizur Rahaman
The conservative reversible logic gate is a special type of parity preserving reversible logic gate which belongs to conservative reversible logic family, having the capability to produce equal number of 1s in output lines as the number of 1s present in input lines. The proposed designs are based on the Fredkin gate which belongs to conservative logic family. It is a 3 × 3 conservative reversible gate with input lines () = {A, B, C} and output lines () = {A, A' C, A' B} having quantum cost 5 [7]. This is shown in Figure 1. As the Fredkin gate belongs to conservative reversible logic family, so it has power to produce equal number of 1s in output lines as the number of 1s present in input lines, which can be clear from the truth table of Fredkin gate, is shown in Table 1.
Energy Efficient and Variability Immune Adder Circuits using Short Gate FinFET INDEP Technique at 10nm technology node
Published in Australian Journal of Electrical and Electronics Engineering, 2023
Umayia Mushtaq, Md Waseem Akram, Dinesh Prasad
FinFET is a non-planner double-gate device, hence removes scaling obstacles to large extent due to the reason that front and back gates can be controlled independently as well (Turi and Delgado-Frias 2017). In addition to power dissipation, estimation of propagation delay in the chip is an important factor. Another parameter called power delay product (PDP) is the product of power consumption and propagation delay. It gives the idea about energy efficiency of a logic gate or logic family in digital electronics. It also gives the estimate of energy consumed per switching event. Therefore, in our circuit design using FinFET at 10 nm technology node, PDP should be low compared to conventional CMOS, resulting in minimum energy consumption.