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Detecting Android Kernel Rootkits via JTAG Memory Introspection
Published in Georgios Kambourakis, Asaf Shabtai, Constantinos Kolias, Dimitrios Damopoulos, Intrusion Detection and Prevention for Mobile Ecosystems, 2017
Mordechai Guri, Yuri Poliak, Bracha Shapira, Yuval Elovici
In this chapter, we present JoKER (JTAG observe Kernel), a system that utilizes the JTAG hardware interface of the mobile device in order to obtain a trusted snapshot of the device memory for the detection of kernel rootkits. The JTAG standard [27] was developed to assist with system testing and postmanufacture debugging of the circuit board. JTAG's connectors are installed on the printed circuit board (PCB) of modern mobile devices such as smartphones and tablets. Our detection system uses two of JTAG's important debugging features: The ability to halt the system instantly by sending special instructions to the main processor.The ability to access the content of the device's volatile memory (RAM) while it is being halted. The overall system does not run on the mobile device, and therefore it can securely read the kernel's memory areas in a trusted manner.
Scan Testing
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
The JTAG standard enables the application of several kinds of tests. This is summarized in the instructions proposed by the standard. These instructions are executed by the TAP controller. As explained in the following list, some of these instructions are mandatory and some are optional. Bypass: It is mandatory. This instruction allows a specific DUT to be tested by bypassing one or more other designs.Extest: This mandatory instruction allows the test of interconnection between two DUT. It is especially useful in the case of integration testing.Intest: This instruction is optional. It can be used to test the internal logic, a block, or a circuit.Sample/Preload: This instruction is mandatory. It helps in taking snapshots of useful data that run during normal operation of the DUT.Icode and Usercode: These two instructions are optional. They allow the access to a specific register known as the device-identification register.RUNBIST: This optional instruction allows the running of a BIST (built-in-self test) solution by using the TAP controller. BIST is explained later.
System and Embedded Core Testing
Published in Perelroyzen Evgeni, Digital Integrated Circuits, 2018
The joint test action group (JTAG) interface is a totality of facilities and operations permitting the user to test VLSIs without physical access to each of their outputs. The testing according to the IEEE Std 1149.1 standard is called boundary scan testing (BST). Such testing is practicable only for chips with an inside set of special elements, that is, the boundary scan cells (BSCs) and their operation control schemes. Later on, the JTAG interface functions were expanded and used extensively in the configurations of programmable logical devices [1, 2, 7].
Sensor integration for real-time data acquisition in aerial surveillance
Published in Australian Journal of Electrical and Electronics Engineering, 2022
Wahyu Rahmaniar, Ardhi Wicaksono Santoso
Table 1 summarises pin connections on FSR, rotors, servo motors, an XBee module, ultrasonic sensors and GPS to the main board. This is shown in (APM 2.5 and Arduflyer V2.5 2013) which includes the ATmega 2560 AVR microcontroller (Atmel 2012) as a processor. ATmega 2560 is a low-power microchip 8-bit AVR RISC-based microcontroller that combines 256KB ISP flash memory, 8KB SRAM and 4KB EEPROM. ATmega 2560 has 86 general purpose I/O lines, 14 pins pulse-width modulations (PWM), 16-channel 10-bit ADC, 4-channel UART/USART, 32 general purpose registers, real-time counters, 6 flexible timer/counters, 2-wire serial interfaces and the JTAG interface for on-chip debugging. The processor sends information about thrust, revolutions per minute (RPM) and direction to the rotor through ESC.
FPGA Realisation of n-QAM Digital Modulators
Published in IETE Technical Review, 2019
J. A. Galaviz-Aguilar, J. C. Nuñez-Perez, F. J. Perez-Pinal, E. Tlelo-Cuautle
The GUI is interfaced with Matlab/Simulink to control the digital modulation on FPGA. It communicates to Matlab to control signals and parameters via JTAG-USB link capabilities, able to write/read data by running Tcl scripts. It also adjusts the data bit streams width at each pulse (BASK, BFSK, BPSK), and control input sequences in n-QAM modulations. Figure 13 shows the modulated outputs for 8-, 16-, and, 64-QAM waveforms. The FPGA resources consumption for BASK, BFSK, BPSK and n-QAM are listed in Table 2, where most of them are consumed by internal memory used for storing the data of signals as well as the PLL circuit for clock generation.
Analysis and Design of Single Stage Bridgeless Cuk Converter for Current Harmonics Suppression Using Particle Swarm Optimization Technique
Published in Electric Power Components and Systems, 2019
Gajendran Marimuthu, Mallapu Gopinath Umamaheswari
The hardware prototype of the 300 watts is constructed and the control algorithm has been implemented using the Texas instruments Code composer studio 5.50 IDE in 32 bit C2000 Piccolo TMS320F28027 DSP microcontroller. It has enhanced control peripherals such as enhanced pulse width modulator, 12 bit ADC with continuous sampling up to 4.6 MSPS. On-board JTAG emulation tool is used for allowing direct interface to a PC for easy programing, debugging and implementation [26, 27]. The converter components are same as that of simulation. The experimental setup is shown in Figure 11 and the hardware implementation is shown in Figure 12.