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Digital Simulation
Published in Luciano Lavagno, Igor L. Markov, Grant Martin, Louis K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, 2017
Logic simulation is the primary tool used for verifying the logical correctness of a hardware design. In many cases, logic simulation is the first activity performed in the process of taking a hardware design from concept to realization. Modern hardware description languages are both simulatable and synthesizable. Designing hardware today is actually writing a program in the hardware description language. Performing a simulation is just running that program. When the program (or model) runs correctly, then one can be reasonably assured that the logic of the design is correct, for the cases that have been tested in the simulation.
Digital Simulation
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC System Design, Verification, and Testing, 2018
Logic simulation is the primary tool used for verifying the logical correctness of a hardware design. In many cases logic simulation is the first activity performed in the process of taking a hardware design from concept to realization. Modern hardware description languages are both simulatable and synthesizable. Designing hardware today is really writing a program in the hardware description language. Performing a simulation is just running that program. When the program (or model) runs correctly, then one can be reasonably assured that the logic of the design is correct, for the cases that have been tested in the simulation.
Ideas for Improving the Digital Design Lab
Published in IETE Journal of Education, 2023
A student may be required to build an up/down counter, a modulo-m counter or a sequence generator as part of a lab experiment. The objectives of such an experiment are as follows. To understand the operation of different types of counters and be able to design a synchronous counter from scratchTo understand why synchronous counters are preferred over asynchronous countersTo understand the process of designing a counter using JK, D, or T flips. This includes finding the excitation tables for J, K, D, or T inputs for each flip-flop and find a minimal product-of-sum expression for each excitation logic.To verify the correctness of the design through simulation There are numerous ways to approach this experiment. One way is to do a paper-and-pencil design and then build the circuit using available flip-flops and logic gates. There is a risk of making an error in the design or in rigging up the circuit. Given that the experiment must be completed in about 3–4 hours, the lab instructor may have to ask the student to come with the design to the class. The students can get the correct design from the instructor and verify the correctness of their own design. In many colleges, the students are given a lab manual where the design is provided. There are also “kits” where a counter design has already been implemented a priori and the student is only required to rig up the circuit and verify its operation. We feel that an intermediate solution, where the student can be assisted with some automation tools for design, may reduce the effort without occluding the learning. While it is possible to use logic synthesis tools and logic simulation tools with test-benches written in a hardware description language, there are two challenges in using HDL – (a) availability of HDL synthesis and simulation tools is not guaranteed, (b) there is a steep learning curve associated with HDL tools. Often, a student may have to spend many hours learning to use the tools. Many colleges overcome this problem by providing a step-by-step procedure to perform the experiment, along with the required files. This approach does not allow the student to assimilate the skills.