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Introduction to Logic Design Using Verilog HDL
Published in Joseph Cavanagh, Verilog HDL Design Examples, 2017
Gate-level modeling using built-in primitives is an intuitive approach to digital design because it corresponds one-to-one with traditional digital logic design at the gate level. Dataflow modeling, however, is at a higher level of abstraction than gate-level modeling. Design automation tools are used to create gate-level logic from dataflow modeling by a process called logic synthesis. Register transfer level (RTL) is a combination of dataflow modeling and behavioral modeling and characterizes the flow of data through logic circuits. The following sections describe different techniques used to design logic circuits using dataflow modeling. These techniques include the continuous assignment statement, reduction operators, the conditional operator, relational operators, logical operators, bitwise operators, and shift operators.
Combinational Circuits
Published in Wen-Long Chin, Principles of Verilog Digital Design, 2022
Combinational and sequential logics are two essential components for the RTL design. A combinational circuit consists of logic gates whose outputs at any time are determined directly from the present combination of inputs without regard to previous inputs and/or outputs, as shown in Figure 5.1. Therefore, there is no notion of storage of information or dependence on values at previous times. There is no clock control as well. Many sophisticated logical functions are realized by combinational circuits.
Processor Modeling and Design Tools
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC System Design, Verification, and Testing, 2018
ADL designers consider two important aspects: the level of abstraction vs. generality. It is very difficult to find an abstraction to capture the features of different types of processors. A common way to obtain generality is to lower the abstraction level. Register transfer level (RTL) is a popular abstraction level — low enough for detailed behavior modeling of digital systems, and high enough to hide gate-level implementation details. Early ADLs are based on RTL descriptions. This section briefly describes a structural ADL: MIMOLA [12].
On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies
Published in International Journal of Electronics, 2022
Pritam Bhattacharjee, Gaurav Trivedi, Alak Majumder
Now whatever the case is – be it DD-CG or AND/OR-CG, as per as the physical design of an IC chip (refer Figure 6) is concerned, these ICG cells are inserted either in backend circuit design or through (viz., register-transfer-level) synthesis Pradeep et al. (2019). Generally, the insertion of ICG cells is not preferred over backend approach due to its inability in providing optimal performance (Donno et al., 2003; Schoenmakers & Theeuwen, 1998). It is important to note over here that the on-chip CG insertion policy do have an impact on how much is pumped inside the chip and the amount of accounted during ACTIVE mode of the chip (Bhattacharjee et al., 2022).
Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform
Published in International Journal of Electronics, 2019
Jai Gopal Pandey, Abhijit Karmakar
The architecture of unsupervised image threshold computation circuit is realized at the register-transfer level using VHDL design language. The design is synthesized using Xilinx ISE tool for the Virtex-5 xc5vfx70 (tff1136-1) FPGA device. A summary of the complete device utilization is given in Table 3. It can be observed that the architecture requires 1.44% (161 out of 11,200) of the FPGA slices for the computation of BCV (8), compute the cumulative mean (3) and moments (13), (14). The architecture requires 2.7% (4 out of 148) of the BRAMs and 3.9% (5 out of 128) of DSP48E slices. The input output block (IOB) utilization of the architecture is 3.3% (21 out of 640).