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Photonic and Advanced Switching Devices
Published in Naoaki Yamanaka, High-Performance Backbone Network Technology, 2020
The first step of the penetration of optical data links into a single-box computer system most likely will be the introduction of optical backplanes to interconnect the multitude of printed circuit boards (PCBs) [24]. For this task, VCSELs obviously are highly attractive light sources. Nevertheless, even if the efficient board-to-board signal transfer was guaranteed, the distribution of highly parallel electrical signals within a single board would continue to impose a significant technological problem already for clock rates as low as 200 MHz. A particularly elegant way for optics to contribute to the removal of the intraboard interconnect bottleneck could be the realization of hybrid electrical-optical PCBs into which polymer waveguides are integrated as an additional optical layer [25]™[27].
Wafer-Level Three-Dimensional Integration for Advanced CMOS Systems
Published in Krzysztof Iniewski, Circuits at the Nanoscale, 2018
Ronald J. Gutmann, Jian-Qiang Lu
Present emphasis on FEOL device technology such as strained layers, high-k gate dielectrics, metallic gates, and wrap-around gate structures is resulting in enhanced digital CMOS devices at the 45 and 32 nm technology nodes. By the 22 nm node, these FEOL enhancements will result in a second-generation interconnect bottleneck (the first being in the 1990s when aluminum (Al) lines, tungsten (W) plugs as interlevel vias, oxide ILDs, and reactive ion etching (RIE) of Al as a patterning process were replaced with Cu lines and interlevel vias, low-k ILDs, and in-laid Cu as a patterning process (Damascene patterning)). Wafer-level 3D is the only near-term alternative to planar (2D) ICs with Cu/lowest-k interconnects, as well as enabling heterogeneous integration of different planar technologies for innovative SoCs (at least further levels of system integration). The technology and infrastructure needs, which must be overcome before, or soon after, a decision to move to large-volume manufacturing, are discussed in this section, and split into technology drivers, design drivers, equipment infrastructure drivers, and industry infrastructure drivers.
Wireless Building Blocks Using SiGe HBTs
Published in John D. Cressler, Circuits and Applications Using Silicon Heterostructure Devices, 2018
In modern silicon technologies, up to eight layers of metal are now used to reduce the “interconnect bottleneck” in digital VLSI circuits. Minimum dimensions are on the order of the metal thickness, which is currently about 0.5 mm for most metal layers, and 1 to 2 mm for top metal supply and ground busses. The shift to multilevel metallization schemes has also led to an increase in the thickness of the intermetal dielectric that separates the top metal layer and the semiconducting substrate (typically 5 to 8 mm). An additional benefit of thicker oxide is lower attenuation for microstrip transmission lines fabricated in production silicon processes, at least in the 1 to 5 GHz range of frequencies. However, the limitations imposed by the interconnecting metals and the conductive substrate continue to constrain the performance of circuits.
Test Architecture Optimization for Post-bond Test and Pre-bond Tests of 3D SoCs Using TAM Reuse
Published in IETE Journal of Research, 2023
Surajit Kumar Roy, Chandan Giri
Three-dimensional (3D) integrated circuits (ICs) have gained considerable interest among the researchers to conquer the interconnect bottleneck in CMOS scaling. In a 3D IC, several dies are stacked one above another vertically. Connections between two layers are provided by vertical interconnects, known as through-silicon-vias (TSVs) [1]. A conceptual view of a 3D IC is presented in Figure 1. Here, the 3D IC contains two layers where each layer includes various design blocks and layers are interconnected by TSVs. Three-dimensional integration offers many benefits over 2D integration [2, 3] like higher performance and reduced power consumption due to the reduced interconnect length, larger bandwidth, heterogeneous integration, and small footprint. Although 3D IC has many benefits, it suffers from several test challenges [4]. Three-dimensional integration can be explored to System-on-Chip (SoC) design, which results in 3D SoC. In a 3DSoC, the cores are placed at several dies. Modular test approach provides testing of cores in 3D SoC using test access mechanism (TAM). The TAM transports test data to the core from the test source and collects test responses from the core to the test sink. It is known that all the test pins are placed at the lower layer of 3D SoC. Hence, TAMs must be extended through TSVs to the upper layers of 3D SoC. But small chip area restricts the number of TSVs and hence, TSV constraint is to be considered during test scheduling. Maximum power limit should also be taken into consideration to prevent chip overheating. Therefore, TAM optimization for 3D IC should consider constraints such as the number of available TSVs, placement of cores in different dies of 3D SoC, and maximum power consumption. It is also known that test architecture optimization to reduce the test time of SoC is an NP-Hard problem [5]. So, the effective test architecture optimization technique is required for 3D SoCs. This inspires to propose a test architecture optimization method for minimizing the test time of 3D SoC for the final complete stack (post-bond test).