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Emerging Interconnect Technologies for 3D Networks-on-Chip
Published in Rohit Sharma, Krzysztof Iniewski, Sung Kyu Lim, Design of 3D Integrated Circuits and Systems, 2018
Designing today’s systems-on-chips (SoCs) that perform functions such as digital signal and graphics processing is a complex exercise [3–5]. Most of these SoCs operate on different clock frequencies, thus becoming distributed systems on a single silicon wafer. This results in a fully distributed communication pattern with no global control. Communication structure in typical SoCs, such as single-chip embedded systems, mobile phones, and HDTVs, could be anything from conventional busbased to dedicated point-to-point links to ad hoc, irregular networks [1]. However, there are multiple concerns with bus-based communication structures, such as parasitic effects, timing control, limited bandwidth, and arbitration delay [6, 7]. Networks, on the other hand, can be preferred over buses because of higher bandwidth, pipelining, and multiple concurrent communication support. Also, dedicated point-to-point links may not be a viable solution, as the number of links may increase much faster with increasing number of cores. For many core systems with much less design cycle time, a shared and segmented global communication structure is essential. This in turn would mean that we come up with a segmented SoC communication structure with shorter wires for better signal integrity and multiplexed buses for increased throughput and lower energy budget. A network-on-chip (NoC) can be seen as a promising solution for optimum SoC design by integration of many cores that provides answers to some of the above-mentioned design challenges [1, 3].
Efficient and Low-Power NoC Router Architecture
Published in Choi Jung Han, Iniewski Krzysztof, High-Speed and Lower Power Technologies, 2018
Network-on-Chip (NoC) architecture provides a communications infrastructure for the cores of a multi-core System-on-Chip (SoC). The NoC resources are connected to the SoC cores enabling them to communicate among each other concurrently by sending messages asynchronously. NoC systems improve the scalability and power efficiency of complex SoCs as compared to other conventional communication systems. Figure 9.1a illustrates an SoC including some IP cores which are connected through a 4 × 5 mesh NoC architecture. The NoC includes a network of switches (routers) which are interconnected by data links. Figure 9.1b illustrates a typical NoC router that consists of some input- and output-ports, an arbiter and a crossbar switch [1]. The input- and output-ports can be simple data buses that connect a router to its channels, but at least one of them should include a circuit to perform buffering and traversal of incoming flits. In all the designs presented in this paper, the input- ports only utilize buffering organization, and the output-ports are simple data buses. A most viable communication mechanism employed in NoCs is packet-based wormhole routing [2]. The messages in wormhole routing are organized as multiple packets where each packet consists of some flits. A flit is a basic unit of data that is generally transferred at clock rate. The first flit of a packet is called the header flit and holds the route information of its associated packet. The remaining flits are called body flits except the last flit, that is called the tail flit. The body and tail flits contain data and can contain two pieces of information: tail state and VC identification.
Conclusion and Future Work
Published in Muhammad Athar Javed Sethi, Bio-Inspired Fault-Tolerant Algorithms for Network-on-Chip, 2020
Network on Chip (NoC) refers to a communication standard for on-chip networks. NoC has replaced the traditional bus and crossbar interconnection of System on Chip (SoC) components. Multiprocessor SoC (MPSoC) is also unable to cope with the globally asynchronous locally synchronous (GALS) communication. Therefore, this leads to the concept of an NoC that can provide the modularity, scalability and efficient reuse of the resources with high bandwidth.
Congestion-aware wireless network-on-chip for high-speed communication
Published in Automatika, 2020
M. Devanathan, V. Ranganathan, P. Sivakumar
In emerging on-chip communication technology, network-on-chip (NoC) has emerged as the communication architecture of complex system-on-chip (SoC) since it has to overcome the problem of reliability, power and speed, which requires high efficiency in bus architecture [1]. By increasing the number of cores of a chip based on the requirement, the NoC architecture faces the communication problem with the distant cores in terms of reliability [2]. As per the International Technology for Roadmap for Semiconductors (ITRS) [3], the wired communication between the cores does not satisfy the interconnection in terms of performance and reliability and a recent research was established as an integrated chip antenna for inter- and intra-chip communication [4]. However, the operating frequency of this silicon-integrated antenna has an energy dissipation problem to establish the communication between the cores. On the other hand, the communication between the distant IP cores causes more latency and power consumption. Since the implementation, it is clear that the performance of the conventional NoC retains the improvement in integrated circuits (IC) performance. This problem initiated the opportunities for the investigation into wireless NoC (WiNoC). This wireless communication technology is suitable to solve the latency and power dissipation issues from the conventional technology, which also eliminates the complexity of interconnection.
Femto power-delay(FPD)super threshold level shifter for network on chip (NoC)
Published in International Journal of Electronics Letters, 2023
Srinivasulu Gundala, M Mahaboob Basha, Rambabu Busi
In recent days, novel low power adders have been introduced for on-chip communications, which work with smaller amount of energy for their operation. The network on chip (NoC) is a network-based communication subsystem on integrated circuit (IC), typically between functional modules in a system on chip (SoC). The functional modules on the IC are typically intellectual property (IP) cores schematising multiple functions of the computer system and are premeditated to be modular in the sense of network science. The NoC is a router-based packet switching network between SoC modules. The NoC technology applies the theory and practices of computer networking to on-chip communication and brings notable improvements over conventional communication architectures (Beigne et al., 2009). The design of SoC and NoC modules with few transistors is the key approach to achieve lower power consumption. The design works fine in an arithmetic unit by consuming low power as well as moderate operating frequency. More recently, NoC cell with an aim of reducing the leakage current results in low leakage power. Total power consumption by such a memory cell is lower. Integration of transistors to get the desired function without affecting the performance of the design (circuit) is the key to its low power requirement (Kaleeswari et al., 2019). In another achievement digital circuits and systems, reducing operating voltage significantly reduces the system level power consumption; on the other hand, reducing supply voltage reduces the system speed, intrinsic gain, linearity, noise margins and driving capabilities (Zhao, 2015; Alioto, 2012). The most suitable in communication application is linear feedback shift register (LFSR) counter analysis using CMOS sub-micrometre, so as to attain smaller chip size with lofty operating speeds and efficient usage of energy. From the results, it is clear that the LFSR counter has additional benefits when compared to other counterparts; therefore, it is a new trendsetter in the field of communication for computing applications (Basha et al., 2012).
A Cross-layer based mapping for spiking neural network onto network on chip
Published in International Journal of Parallel, Emergent and Distributed Systems, 2018
Information processing in the mammalian brain has become one of the most attractive fields for neuro-researchers. The basic processing elements in mammalian brain are neurons which exchanges information with each other in the form of pulses. Each neuron connects to other neurons through synaptic connections. There are thousands number of synapses per neuron and the average number in some mammals is about 8K. Spiking neural networks (SNNs) offer a powerful brain-inspired computational method to emulate biological information processing than the previous artificial neural networks [1]. For massive neural interconnections, the traditional bus-based topology is not flexible and scalable for inter-neuron spikes transmission. To overcome the above problems, packet-switch based Network-on-Chip (NoC) is presented as an efficient paradigm. The advantages of adopting NoC as neural interconnection architecture have been described in the previous research works [2–5]. Every process elements (PEs) within on-chip network adopts packets to transfer data through inter-node channels. Similarly, neurons in SNNs connect with each other by synaptic connections and transfer biological information by spikes. The design of NoC places great emphasis on communication rather than computation [6]. When massive neurons are connected by NoC and the scale of NoC increasing, the inter-neuron communication will be more important than computation of each on-chip network node. To reduce inter-neuron communication cost, some NoC-based SNNs integrate a scale number of neurons into a same network core which is also regarded as a neural array using time division multiplexing technology [2,7–10]. For these neuromorphic systems, the maximum number of implemented neurons is fixed and it is necessary to adopt several neural arrays for achieving large scale SNN-based applications. In addition, different applications require different inter-neuron topology and communication overhead [11]. Therefore, efficient neural mapping strategies are critical in the aspect of mapping neurons to proper on-chip network node, which supports to improve inter-neuron communication efficiency and whole neuromorphic system performance.