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Parallel Computation of Quotients and Partial Remainders to Design Divider Circuits
Published in Hafiz Md. Hasan Babu, VLSI Circuits and Embedded Systems, 2023
Re-configurable computing has explored a new dimension of computing architecture since its inception in 1960. Re-configurable computing is a computer architecture which combines some of the flexibility of software with the high performance of hardware by processing with a very flexible high speed computing fabrics like field-programmable gate arrays (FPGAs). The principal difference when compared to using ordinary microprocessors is the ability to make substantial changes to the data path itself in addition to the control flow. On the other hand, the main difference with custom hardware, i.e., application-specific integrated circuits (ASICs) is the possibility to adapt the hardware during run time by “loading” a new circuit on the re-configurable fabric. Their functionality can be upgraded and repaired during their operational life cycle and specialized to the particular instance of a task. Sometimes, they are the only way to achieve the required real-time performance without fabricating custom integrated circuits. The implementation of FPGA has been widely seen in many applications including signal processing, cryptography, processing, scientific computation and arithmetic computing.
An Overview of High-Performance Computing Techniques Applied to Image Processing
Published in Sandeep Saini, Kusum Lata, G.R. Sinha, VLSI and Hardware Implementations Using Modern Machine Learning Methods, 2021
Giulliano Paes Carnielli, Rangel Arthur, Ana Carolina Borges Monteiro, Reinaldo Padilha Franca, Yuzo Iano
Exemplifying FPGA applications, it is possible to stand out in the electric sector, for digital signal processing in real time; multimedia sector, for image processing in real time and high performance; telecom sector, in high-performance switches and routers; since FPGA chips are used for numerous applications, ranging from video games to areas such as aerospace, prototyping, HPC, medical, among others. It is possible to find the use of FPGA in applications for audio in circuits of DACs (digital to analog converter) where several aspects are modified to achieve a better reproduction of the sound, or even by alternative consoles using FPGA chips to reproduce via hardware the same quality as the original versions of video games, or even FPGA chips still allow the player the flexibility to play games from different consoles using a single device [52].
Introduction
Published in Heqing Zhu, Data Plane Development Kit (DPDK), 2020
FPGA is a semi-custom circuit in the ASIC domain. Unlike ASIC, FPGA is programmable and flexible to use. FPGA is inherently parallelized. Its development method greatly differs from the software. FPGA developers require an in-depth understanding of hardware description language (Verilog or VHDL). The general software executes in the sequential order on the general-purpose processor; the software parallelism is up to the software design. FPGA silicon can include some fixed functions and some programmable functions. FPGA has made great progress in the data center in the recent years, and FPGA can be used as a cloud service. FPGA can be used for smart NIC. FPGA is often selected to build the super-high-speed I/O interface, advanced packet parsing and flow filtering, and QoS acceleration. FPGA can be offered as add-in card; through PCIe interface, it is easy to be plugged into the server system; it is popular for cloud data center scenario. FPGA can also be used for a specific purpose, like signal processing. FPGA is also often used in a special board design.
Parallel computing in railway research
Published in International Journal of Rail Transportation, 2020
Qing Wu, Maksym Spiryagin, Colin Cole, Tim McSweeney
A FPGA is a reconfigurable and programmable digital chip that can be set up to control multiple computing units (CPUs, GPUs or others) in parallel. It provides an array of uniform Configurable Logic Blocks and Input/Output Blocks that can be programmed to form different circuits as designers want. It offers significant configuration flexibility and a large number of gate resources which contribute to its great capability of parallel computing. For example, researchers can programme eight of exactly the same circuits (on the same chip) that are connected to eight computing cores. Parallel computing can then be conducted by sending the computing cores parallelised computing tasks. Also, different circuits can be programmed and then connected to different computing cores, so that the FPGA and the computing cores can then be used to compute different computing tasks but still in a parallel fashion. Applications of parallel computing using FPGAs have been reported [59–62]. Most commonly, FPGAs are used to achieve real-time signal processing or real-time hardware-in-loop applications.
A Bio-Inspired, Self-Healing, Resilient Architecture for Digital Instrumentation and Control Systems and Embedded Devices
Published in Nuclear Technology, 2018
Shawkat S. Khairullah, Carl R. Elks
Each fault reading unit embedded inside the external healing layer (top or bottom) can produce 12 control signals for the recovery of one to four faulty T cells located in the tissue layer, and the healing action circuit selects which two of these four syndromes generating three signals will be used to configure the two embryonic stem cells located either in the top external healing layer or in the bottom external healing layer. This configuration process is based on the location of fault occurrence in the BioSymPLe architecture. BioSymPLe is an architectural concept that leverages existing programmable and configurable hardware technologies such as FPGA technology and application-specific integrated circuits. Many studies (and marketplace products) have confirmed that FPGA technology is a viable and competitive option for various application domains (aerospace, nuclear industry) and industrial control systems due to their characteristics with regard to reprogrammability, high performance, concurrency, and low-cost development.16–18 As a consequence, hardware implementation of this proposed architecture is realized on FPGAs.
A Review on SEU Mitigation Techniques for FPGA Configuration Memory
Published in IETE Technical Review, 2018
T. S. Nidhin, Anindya Bhattacharyya, R. P. Behera, T. Jayanthi
Three categories of upsets experienced by the SRAM-based FPGAs are (1) static configuration bitstream upset, (2) dynamic upset (either transient or upset of a user memory cell), and (3) functional upset (e.g. configuration circuit or JTAG tap controller). Reconfiguration is the process of post configuration memory write, which is the most efficient way to mitigate these upsets. Reconfiguration can be either partial or full; full reconfiguration will completely replace the configuration bitstream and PR modifies a fraction of the resources. PR can be categorised as static and dynamic. The static PR modifies a portion of the FPGA while the entire FPGA remains inactive and non-operational, however, the dynamic PR occurs while the device is active and operational. PR reduces the configuration time and store memory as the PR files are smaller than full ones [20,21].