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Defining Varied Modeling Techniques Using DEVS
Published in Gabriel A. Wainer, Discrete-Event Modeling and Simulation, 2017
VHDL is a hardware description language that has become very popular in the field of design of digital circuits and was standardized by the IEEE. The standard VHDL-AMS (IEEE Standard 1076.1) included extensions to model mixed-signal circuits [11]. The basic component is the design entity declaration, which describes the interface to a VHDL-AMS design unit:
Process validation test of CNTFET using Stanford model
Published in International Journal of Electronics, 2022
Hamed Sarbazi, Reza Sabbaghi-Nadooshan, Alireza Hassanzadeh
For analysing complex circuit designs, first, they should be modelled in an appropriate language, and then, their behaviour can be investigated by simulation. One important problem in the analysis is the absence of high-level abstract equations. In electrical/electronic domain, the netlist of a circuit can be described using the SPICE simulator or its derivatives. However, interaction effects or cross-coupling in terminal pairs are neglected in SPICE. This may lead to adverse results in the final design with regard to the performance and design time. Hence, such effects can be eliminated by behavioural modelling in powerful languages such as VHDL-AMS and Verilog AMS. The components of a digital system can be described by hardware description languages with the help of words and symbols instead of using a block or logic diagram. Behavioural description in the highest level of a VLSI design describes architectural features of the system. Many CNTFET models have been developed both theoretically and experimentally. In many analogues and digital applications, CNTFETs are common in nanodevices(Ashenden et al., 2002).
The structural index of sensitivity equation systems
Published in Mathematical and Computer Modelling of Dynamical Systems, 2018
Atiyah Elsheikh, Wolfgang Wiechert
The recent decades encountered a tremendous progress in the field of multidisciplinary simulation tools for continuous time discrete variable systems. A new generation of universal tools and languages for modelling and simulation multi-physical domain applications as for example Modelica [1], VHDL-AMS [2] and others emerged and became widely accepted. Although this development is still in progress, commercial and academic high-quality implementations are available and broadly used, cf. www.modelica.org/tools.
Functional verification of a sigma-delta ADC real number model
Published in International Journal of Electronics, 2022
Nikolaos Georgoulopoulos, Prof. Alkis Hatzopoulos
In Table 3, the parameter values of the Order, Amplitude, Modulator frequency and SNR are either set or computed inside the sigma-delta ADC RNM model or the top-level module of the proposed verification architecture. To be more precise regarding SNR computation, the SNR for the sigma-delta ADC RNM model is calculated from the following equation, which computes the SNR for a first-order SDM: (Reiss, 2008), where A is the amplitude, b are the bits of the quantiser, covering the range from – V to +V, and r is the rate of the OSR. The VHDL-AMS reference model’s SNR is referred to in the work of Szermer et al. (2003). Reusability, reconfigurability, modularity and interoperability have a rating scale from the lowest level (1), meaning that the verification architecture displays poor levels of a certain parameter, to the highest level (5), meaning that the testbench demonstrates high grades of a specific parameter. It is essential to note that the rating of the aforementioned parameters is based on observations. Regarding reusability, the proposed verification testbench can be reusable without modifying it significantly for any other project or a mixed-signal SoC architecture which might include a sigma-delta ADC model as its submodule. In terms of reconfigurability, the presented architecture holds again a high level, with respect to the reference testbenches, because it can support verifying multi-bit sigma-delta ADCs or higher order modulators, with a minor reconfiguration. Moving next to modularity, the proposed architecture continues to meet high standards due to the fact that multiple test cases can utilise the same environment for full mixed-signal functional verification. Concerning interoperability between submodules implemented with different modelling approaches and between various commercial verification suites, the presented UVM-based testbench displays great improvement compared to the reference ones, mainly because of the UVM features exploitation.