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Introduction to Hardware Description Languages
Published in Suman Lata Tripathi, Sobhit Saxena, Sushanta Kumar Mohapatra, Advanced VLSI Design and Testability Issues, 2020
Shasanka Sekhar Rout, Salony Mahapatro
In analog and mixed-signal (A&MS) systems, Verilog-AMS plays as a behavioral language. It is a derivative from IEEE standard 1364-2005 Verilog HDL. It also captures the entire IEEE standard 1364-2005 Verilog HDL specification, analog equivalent for explaining analog systems (Verilog-A), and extensions together for mentioning the full Verilog-AMS. Verilog-AMS focuses on the designers of (A&MS) systems, IC creation, and applying of modules for high-level behavioral and structural descriptions of systems. It is applicable to both electrical and nonelectrical systems explanation as well as supportive for conservative and signal flow explanation.
Process validation test of CNTFET using Stanford model
Published in International Journal of Electronics, 2022
Hamed Sarbazi, Reza Sabbaghi-Nadooshan, Alireza Hassanzadeh
For analysing complex circuit designs, first, they should be modelled in an appropriate language, and then, their behaviour can be investigated by simulation. One important problem in the analysis is the absence of high-level abstract equations. In electrical/electronic domain, the netlist of a circuit can be described using the SPICE simulator or its derivatives. However, interaction effects or cross-coupling in terminal pairs are neglected in SPICE. This may lead to adverse results in the final design with regard to the performance and design time. Hence, such effects can be eliminated by behavioural modelling in powerful languages such as VHDL-AMS and Verilog AMS. The components of a digital system can be described by hardware description languages with the help of words and symbols instead of using a block or logic diagram. Behavioural description in the highest level of a VLSI design describes architectural features of the system. Many CNTFET models have been developed both theoretically and experimentally. In many analogues and digital applications, CNTFETs are common in nanodevices(Ashenden et al., 2002).
Functional verification of a sigma-delta ADC real number model
Published in International Journal of Electronics, 2022
Nikolaos Georgoulopoulos, Prof. Alkis Hatzopoulos
Commonly, digital IC applications took advantage of UVM effectiveness, with features including verification planning, concurrent and immediate assertions, coverage metrics and constrained-random stimuli. For the analog elements of a mixed-signal circuit, directed testing, corner analysis and Monte Carlo simulation were utilised as a traditional verification approach. Nevertheless, the absence of advanced automated verification concepts in state-of-the-art analog solvers sometimes leads the industry to other solutions. Real Number Modelling (RNM) and UVM play a significant role in the creation of efficient mixed-signal functional verification architectures (Barros et al., 2018; Georgoulopoulos et al., 2018, 2019; Logaras et al., 2017; Ramirez et al., 2019; Simon et al., 2017). RNM is a mixed-signal modelling approach which represents the analog signals as real number variables (Louis et al., 2019; Lim & Horowitz, 2019; Wang et al., 2009; Joeres et al., 2007; Vogelsong et al., 2015; Georgoulopoulos and Hatzopoulos, 2019; Cadence Design Systems, 2015), and it is available in SystemVerilog, Verilog-AMS and VHDL-AMS. Apart from that, it utilises the digital solver to solve the system at discrete time points, in order to achieve higher simulation performance with respect to other traditional analog/mixed-signal (AMS) modelling methods (Brinson et al., 2012; Brinson & Nabijou, 2011; Hernández & Canesin, 2012; Jamil et al., 2004; Ksentini et al., 2006; Lee & Hattori, 2009; Li et al., 2015; Pecheux et al., 2005; Sánchez De La Vega & Tlelo-Cuautle, 2015; Szermer et al., 2003; Tlelo-Cuautle et al., 2007).