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The Integrated Circuit Design Process and Electronic Design Automation
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC System Design, Verification, and Testing, 2018
Robert Damiano, Raul Camposano
The product team partitions the SLD into functional units and hands these units to the circuit design teams. The circuit designers describe the functional intent through a high-level design language (HDL). The most popular HDLs are Verilog and VHDL. SystemVerilog is a new language, adopted by the IEEE, which contains design, testbench, and assertion syntax. These languages allow the circuit designers to express the behavior of their design using high-level functions such as addition and multiplication. These languages allow expression of the logic at the register transfer level (RTL), in the sense that an assignment of registers expresses functionality. For the analog and analog mixed signal (AMS) parts of the design, there are also high-level design languages such as Verilog-AMS and VHDL-AMS. Most commonly, circuit designers use Simulation Program with Integrated Circuit Emphasis (SPICE) transistor models and netlists to describe analog components. However, high-level languages provide an easier interface between analog and digital segments of the design and they allow writing higher-level behavior of the analog parts. Although the high-level approaches are useful as simulation model interfaces, there remains no clear method of synthesizing transistors from them. Therefore, transistor circuit designers usually depend on schematic capture tools to enter their data.
Integrated Circuit Design Process and Electronic Design Automation
Published in Luciano Lavagno, Igor L. Markov, Grant Martin, Louis K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, 2017
Robert Damiano, Raul Camposano, Grant E. Martin
The product team partitions the SLD into functional units and hands these units to the circuit design teams. The circuit designers describe the functional intent through a high-level design language (HDL). The most popular HDLs are Verilog and VHDL. SystemVerilog is a recent language, adopted by the IEEE, which contains design, testbench, and assertion syntax. These languages allow the circuit designers to express the behavior of their design using high-level functions such as addition and multiplication. These languages allow expression of the logic at the register transfer level (RTL), in the sense that an assignment of registers expresses functionality. For the analog and analog mixed signal (AMS) parts of the design, there are also HDLs such as Verilog-AMS and VHDL-AMS. Most commonly, circuit designers use Simulation Program with IC Emphasis (SPICE) transistor models and netlists to describe analog components. However, high-level languages provide an easier interface between analog and digital segments of the design, and they allow writing higher-level behavior of the analog parts. Although the high-level approaches are useful as simulation model interfaces, there remains no clear method of synthesizing transistors from them. Therefore, transistor circuit designers usually depend on schematic capture tools to enter their data.
Functional verification of a sigma-delta ADC real number model
Published in International Journal of Electronics, 2022
Nikolaos Georgoulopoulos, Prof. Alkis Hatzopoulos
UVM is an IEEE methodology standard (IEEE 1800.2–2017) for IC designs verification boosted by SystemVerilog, having as goal to create verification components for transaction-level modelling (TLM) for more efficient communication between the components (Accellera, 2015). A base class library forms its spinal cord, making it suitable for constructing Universal Verification Components (UVCs). UVC is basically a concept of the stimuli generation, checking, monitoring and coverage gathering mechanisms for design, protocol, module verification, etc. Furthermore, depending on the design under test (DUT), a UVC can consist of one or more agents where each agent can connect via a specific interface to the DUT for verifying whole or part of its functionality.