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Application-Specific Integrated Circuits
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
M. Michael Vai, William S. Song, Brian M. Tyrrell
More recently, other “higher-level” design languages (e.g., SystemC, online at http://www.systemc.org) have allowed for more powerful design approaches at the behavioral level, thus allowing for effective conceptualization of larger systems. One major benefit of SystemC is that it allows for more hardware/software co-design. The SystemVerilog extension of the Verilog HDL allows for a co-simulation of Verilog and SystemC blocks. Verilog analog mixed-signal (AMS) extensions have also been developed to support the high-level abstraction of analog and mixed-signal circuits in a system.
Process validation test of CNTFET using Stanford model
Published in International Journal of Electronics, 2022
Hamed Sarbazi, Reza Sabbaghi-Nadooshan, Alireza Hassanzadeh
For analysing complex circuit designs, first, they should be modelled in an appropriate language, and then, their behaviour can be investigated by simulation. One important problem in the analysis is the absence of high-level abstract equations. In electrical/electronic domain, the netlist of a circuit can be described using the SPICE simulator or its derivatives. However, interaction effects or cross-coupling in terminal pairs are neglected in SPICE. This may lead to adverse results in the final design with regard to the performance and design time. Hence, such effects can be eliminated by behavioural modelling in powerful languages such as VHDL-AMS and Verilog AMS. The components of a digital system can be described by hardware description languages with the help of words and symbols instead of using a block or logic diagram. Behavioural description in the highest level of a VLSI design describes architectural features of the system. Many CNTFET models have been developed both theoretically and experimentally. In many analogues and digital applications, CNTFETs are common in nanodevices(Ashenden et al., 2002).
Functional verification of a sigma-delta ADC real number model
Published in International Journal of Electronics, 2022
Nikolaos Georgoulopoulos, Prof. Alkis Hatzopoulos
Commonly, digital IC applications took advantage of UVM effectiveness, with features including verification planning, concurrent and immediate assertions, coverage metrics and constrained-random stimuli. For the analog elements of a mixed-signal circuit, directed testing, corner analysis and Monte Carlo simulation were utilised as a traditional verification approach. Nevertheless, the absence of advanced automated verification concepts in state-of-the-art analog solvers sometimes leads the industry to other solutions. Real Number Modelling (RNM) and UVM play a significant role in the creation of efficient mixed-signal functional verification architectures (Barros et al., 2018; Georgoulopoulos et al., 2018, 2019; Logaras et al., 2017; Ramirez et al., 2019; Simon et al., 2017). RNM is a mixed-signal modelling approach which represents the analog signals as real number variables (Louis et al., 2019; Lim & Horowitz, 2019; Wang et al., 2009; Joeres et al., 2007; Vogelsong et al., 2015; Georgoulopoulos and Hatzopoulos, 2019; Cadence Design Systems, 2015), and it is available in SystemVerilog, Verilog-AMS and VHDL-AMS. Apart from that, it utilises the digital solver to solve the system at discrete time points, in order to achieve higher simulation performance with respect to other traditional analog/mixed-signal (AMS) modelling methods (Brinson et al., 2012; Brinson & Nabijou, 2011; Hernández & Canesin, 2012; Jamil et al., 2004; Ksentini et al., 2006; Lee & Hattori, 2009; Li et al., 2015; Pecheux et al., 2005; Sánchez De La Vega & Tlelo-Cuautle, 2015; Szermer et al., 2003; Tlelo-Cuautle et al., 2007).
A Low-Power VLSI Implementation of RFIR Filter Design using Radix-2 Algorithm with LCSLA
Published in IETE Journal of Research, 2020
Kasarla Satish Reddy, Hosahally Narayangowda Suresh
From these graphs, it is clear that the performance of the FPGA has been improved in the RFIR filter design based on the Radix2-LCSLA method compared to the existing RFIR filter designs. Figure 12 represents the diagram of RTL schematic of 8B and 3 T for RFIR filter design. This RTL schematic design was taken from the Synplify pro software by using the Verilog code. This architecture has a separate code for each block such as LCSLA, Radix2, counter, reg bank, GRPPG, and an accumulator. Generally, the input value of the multiplication operation with a coefficient provides the output through pipeline shift add tree. Figure 13 shows the RTL schematic of RFIR-Radix2-CSLA filter design for 8B&3 T for180 nm technology, which is taken from the Cadence tool. For ASIC implementation, same the Verilog code has been employed for FPGA implementation. The Cadence RTL compiler is utilized to convert RTL Verilog into gate-level Verilog. The Verilog code is read by employing a Tcl file and corresponding libraries are set in the Tcl file. After the synthesis process the performance parameters of area, power and delay values measured with the help of cadence tool. Finally, the total number of the area, power and delay are mitigated in the RFIR-Radix2-LCSLA method compared to the existing methods.