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Digital Layout — Placement
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
In addition to the previous trends, a number of practical issues arise in modern day designs that should be handled by placers. These include: Flat placement of 10 million components in mixed-mode designs. Modern designs typically require a number of placement iterations to achieve timing closure. These iterations routinely consume enormous amounts of time — a number of days — till completion. Thus it is necessary to have fast and efficient placement algorithms. Furthermore, components of modern designs include movable cells and movable and fixed blocks. All these need to be smoothly and efficiently handled by the placer.Given the ubiquitous presence of mobile devices, temperature- and power-driven placement where the objective is to reduce the total power consumption as well as to smooth temperature differences between spatially proximate regions, is getting increasingly important.Placement-driven synthesis, where placement is used to derive logic synthesis optimizations [76–78].
Design-for-Test
Published in Luciano Lavagno, Igor L. Markov, Grant Martin, Louis K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, 2017
At-speed testing with logic BIST essentially follows the same scheme as at-speed testing with ATPG patterns. (Historical note: contrary to frequent assertions by logic BIST advocates that pseudorandom pattern logic BIST is needed to enable at-speed testing, ATPG-based at-speed test has been practiced long before logic BIST became popular and is still being used very successfully today.) Most approaches use slow scan (to limit power consumption, among other things) followed by the rapid application of a short burst of at-speed edge events. Just as with ATPG methods, the scan and at-speed edge events can be controlled directly by test equipment or from an OPCG macro. The advantage of using slow scan is that the PRPG/MISR and other scan-switching and interface logic need not be designed for high speed. That simplifies timing closure and gives the placement and wiring tools more flexibility. Placement/wiring consideration may still favor using several smaller, distributed PRPG/MISR macros. Modern DFTS, DRC, fault grading, and signature-simulation tools for logic BIST generally allow for distributed macros.
Timing-Driven Placement
Published in Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 2008
David Z. Pan, Bill Halpin, Haoxing Ren
It shall be noted that to achieve the overall timing closure, TDP needs to work closely with synthesis/optimization tools (such as buffer insertion and gate sizing) and routing (in particular global routing). The entire physical design/synthesis closure is an extremely complex task. Furthermore, modern complex SOC designs usually have multiple clock domains, or even multiple cycle paths, which make the TDP problem even more complicated. Because of the infrastructure limitation, the academia has not been able to fully push the state of the art and limits of TDP. With the availability of OpenAccess [64] and the OpenAccess gear timer [65,66], it is possible to push the frontier of the very successful International Symposium on Physical Design (ISPD) placement contest [63] for university researchers to work on more realistic timing objectives. As technology scales into sub100 nm regimes, new physical and manufacturing effects, in particular leakage/power and variations, have to be considered together with timing closure during TDP [67,68], which requires continuous innovations for better quality and productivity.
Timing Closure Problem: Review of Challenges at Advanced Process Nodes and Solutions
Published in IETE Technical Review, 2019
Sneh Saurabh, Hitarth Shah, Shivendra Singh
Traditionally, following strategies are employed to mitigate the problem of timing closure: Introduce pessimism in the early phases of a design: Though the goal of timing closure is to meet timing constraints at the end of a design flow, static timing analysis (STA) is carried out at individual design steps of Figure 1(a). This ensures that timing-critical portion of a design can be optimized for better timing during early stages of a design flow, thus mitigating the timing closure problem. The difficulty in finding actual timing-critical portion of a circuit during early phases of a design flow is handled by taking a pessimistic view of the design attributes such as wire-delay or by putting additional timing margins [2,6,7]. These strategies compensate the lack of information in early phases of a design flow by over-designing, which often results in an increased area and power [2].Predict and prevent: One of the strategies to mitigate timing closure problem is by predicting the timing problems early in a design flow and taking preventive measures to avoid them [8,9]. This strategy can be implemented in various ways depending on the information content of a design [2,8,9]. For example, logic synthesis can take its decisions based on estimated interconnect delays [9]. The predictability of interconnect delays can be improved by keeping a companion placed-cell model or by interleaving logic synthesis with placement [2]. The effectiveness of “predict and prevent” strategies depend on the correlation between the estimated design attributes and the actual design attributes computed in the later phase of a design flow. Practically, ensuring this correlation is difficult.Timing-driven implementation engines: The timing closure problem can be mitigated by making the implementation engines take their decisions based on circuit timing. For example, a timing-driven placement engine internally invokes STA engine to find critical paths in the design [3,10]. Subsequently, it assigns higher weights to nets that are more timing-critical [3,11]. As a result, gates connected with the critical nets are placed together, reducing the delay of the critical path. Similarly, timing-driven buffer insertion and routing can mitigate the timing closure problem [12–14].