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Digital Logic Gates
Published in Dale Patrick, Stephen Fardo, Vigyan ‘Vigs’ Chandra, Electronic Digital System Fundamentals, 2020
Dale Patrick, Stephen Fardo, Vigyan ‘Vigs’ Chandra
An AND gate is designed to have two or more inputs and one output. Essentially, if all inputs are in the 1 state simultaneously, then a 1 will appear in the output. Figure 2-1 shows a simple switch-lamp circuit of the AND gate, its symbol, and an operational table. In Figure 2-1(a), a switch turned on represents a 1 condition, whereas off represents a 0. The lamp also displays this same condition by being a 1 when it is on and 0 when turned off. Note that the switches are labeled A and B, whereas the lamp, or output, is labeled C. The operational characteristics of a gate are usually simplified by describing the input-output relationship in a table. The table in Figure 2-1(c) shows the 1 and 0 alternatives at the input and the corresponding output that will occur as a result of the input. As a rule, such a description of a gate is called a truth table. Essentially, it shows the predictable operating conditions or a logic circuit.
Digital Design—Combinational Logic
Published in Bogdan M. Wilamowski, J. David Irwin, Fundamentals of Industrial Electronics, 2018
Buren Earl Wells, Sin Ming Loo
It can be shown that any combinational function can be implemented using a combination of the basic AND, OR, and NOT operators. The corresponding set of gates is easily implemented in digital hardware in a manner that is dependent upon the underlying device technology. In Boolean algebra, a truth table can be used to show the values of the output for all possible values of the set of inputs. An example of the truth tables for all three of these main types of gates is shown in Figure 20.2. An AND gate is characterized by the fact that all inputs must be at a logic 1 before the output is a 1. An OR gate is characterized by the fact that if any of the inputs are at a logic 1, then the output is also at a logic 1, and a NOT gate simply inverts (switches) the value of its logic input. The functionality of applying the logic operations on the set of inputs to produce an output can also be expressed using Boolean algebra notation. In this notation, the input and outputs of a logical network are represented as variables or constants in much the same way as conventional algebraic statements. The operations performed by these three gates are expressed using standard algebraic symbols, where the AND operation represents Boolean multiplication, and the OR operation represents Boolean addition. By definition, the NOT operation is a unary operator. It is expressed by putting a line over the variable of interest.
Integrated Circuits
Published in Jerry C. Whitaker, Microelectronics, 2018
To optimize the gate level design, let us look at the performance of a single CMOS inverter as shown in Fig. 5.1. Delay of a gate is typically defined as the time difference between input transition and output transition at 50% of supply voltage. The inverter gate delay can be analytically expressed as Td=Cl(An/βn+Ap/βp)/2
An Online Course Content for Undergraduate Students on Full-Custom Design of a Digital VLSI Circuit Using Open-Source Software
Published in IETE Journal of Education, 2023
A CMOS digital circuit implements a complement logic function, for example, CMOS-based NAND gate is a complement of AND function, and CMOS-based NOR gate is a complement of OR function. It is noteworthy that the NAND-NOR comprises a PULL-UP network (realized by pMOS which passes strong 1-logic, i.e. VDD) and PULL-DOWN network (realized by nMOS which passes strong 0-logic, i.e. Ground). The PULL-UP networks are required to charge the output node to VDD. Whereas PULL-DOWN networks are needed to discharge the output node to the Ground. In this way the output node of a digital gate swings between VDD and Ground giving strong logic. A strong logic is a signal when it approaches near power supplies or rails (i.e. VDD and Ground). Under such conditions, the signal can source or sink maximum current.
A Novel Slice-Based High-Performance ALU Design Using Prospective Single Electron Transistor
Published in IETE Journal of Research, 2022
Rashmit Patel, Yash Agrawal, Rutu Parekh
The design of AL slice is shown in Figure 4. The AL slice is designed with SET-based inverter, NAND gate, NOR gate, and combination of these gates. The hardware design of the AL slice shows that it performs operation on two input signals, “A” and “B”. The AL slice performs desired operation based on the five input control signals, namely “sel_neg”, “sel_op1”, “sel_op2”, “shift_r”, and “force_carry1”. Table 1 describes each control signal value for specified instruction. The “carry_prev” and “Anext” are cascade inputs that are used to cascade multiple AL slices. Based on the values of input, control and cascade signals, the AL slice generates “carry” and “result” outputs. The “carry” and “carry_prev” are inverted polarity signals. Each AL slice comprises 74 SETs.
An improved Random Swapping Thermometer Coding (RSTC) Dynamic Element Matching (DEM) method
Published in International Journal of Electronics Letters, 2021
Mohammadreza Armuti, Mehdi Bandali, Omid Hashemipour
In this design, the N-Bit NAND gate employs just one stage of CMOS logic in its structure. If the N-Bit NAND gate employs more stages of CMOS logic, the number of MOSFETs of it increases and as a result, the complexity of N-Bit XNOR gate increases. According to Figures 4–7, it is obvious that the complexity increment of N-Bit XNOR gate leads to a higher complexity difference between the proposed structure and the possible structure of ”RSTC with restricted jumping technique”.