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Semiconductors and Digital Logic
Published in Syed R. Rizvi, Microcontroller Programming, 2016
Table 2.5 summarizes the action of an OR gate. Binary 0 stands for low voltage, and binary 1 for high voltage. Notice that one or more high inputs produces a high output, and that is the reason why this circuit is called an OR gate. Figure 2.16 (b) shows a 3-input OR gate. If all inputs are low, all diodes are off and the output is 0. If one or more inputs are high, the output is high. Table 2.5 illustrates the OR gate truth table. An OR gate can have as many inputs as desired. Just add one diode for each additional input. Seven diodes result in a 7-input OR gate, 10 diodes in a 10-input OR gate. No matter how many inputs, the action of any OR gate is to produce HIGH output if one or more inputs are high. Bipolar transistors and MOSFETs can also be used to build OR gates. No matter what devices are used, OR gates always produce a high output when one or more inputs are high. Best Practice: When constructing a truth table, always list the input words in a binary progression like 000, 001, 010, … 111. This guarantees that all input possibilities will be accounted for. It also improves the readability of the truth table.
Basic elements of combinational logic
Published in J. R. Gibson, Electronic Logic Circuits, 2013
This element is another one which implements a fundamental definition in Boolean algebra. The OR gate is the combinational logic circuit which has any number of inputs and has an output of 1 when any one, or more than one, of the inputs is 1. An alternative statement is that the circuit gives the output 1 unless all the inputs are 0, in which case it gives the output 0. Note that the output of a two-input OR circuit is not just 1 in the cases input A is 1 with B equals 0, or input B is 1 with A equals 0; it also includes the situation where A and B are both 1 (i.e. A is 1 or B is 1 or A and B are both 1). From this description the truth table can be constructed; Table 2.5 is that for a three-input OR gate.
Integrated Circuits
Published in Jerry C. Whitaker, Microelectronics, 2018
To optimize the gate level design, let us look at the performance of a single CMOS inverter as shown in Fig. 5.1. Delay of a gate is typically defined as the time difference between input transition and output transition at 50% of supply voltage. The inverter gate delay can be analytically expressed as Td=Cl(An/βn+Ap/βp)/2
A novel integrated method of fsQCA and digital design for sustainability monitoring and assessment in building energy management systems: a case study
Published in Journal of Building Performance Simulation, 2023
Abdolvahhab Fetanat, Mohsen Tayebi, Gholamreza Shafipour, Mehran Moteraghi
In Figure 10, the horizontal and vertical lines indicate the time and changing signals between the two levels. The down-level shows logic 0, the up-level indicates logic 1. The output of AND gate has logic 1 when the input signals are logic 1. The OR gate has output 1 when one of the input signals is logic 1. The NOT gate is usually called the inverter. It is shown that the output signal reverses the concept of the input. It should be noted that the AND gate and OR gate may have more than two inputs. For example, the AND gate with three inputs and one OR gate with four inputs are indicated in Figure 11. The AND gate with three inputs has output 1 when three inputs are logic 1. The output of the AND gate is logic 0 when all three inputs are logic 0. The OR gate with four inputs has output 1 when one of the inputs be in logic 1. When the output of the OR gate has logic 0 that all inputs are in logic 0 (Mano and Ciletti 2012).
Investigation of extremely severe traffic crashes using fault tree analysis
Published in Transportation Letters, 2020
Chengcheng Xu, Chen Wang, Yulei Ding, Wei Wang
A fault tree uses the standard logic symbols to interconnect the contributory events. A typical fault tree illustrated in Figure 2 includes a number of different logic symbols. A rectangle in a typical fault represents the top event or intermediate event. The top event refers to the undesirable event to be studied. In this study, the top event is defined as the occurrence of extremely severe traffic crashes. In a fault tree, all the paths flow toward to the top event. The intermediate event is the input event of its upper-level event and the output event of its lower-level event. A circle at the bottom level of a fault tree represents a basic event that is a basic initiating fault. The OR- and AND-gates are the two basic types of fault tree gates. The OR-gate is equivalent to the Boolean symbol of +. The event above an OR-gate occurs when one or more of the input events attached to the OR-gate occur. The AND-gate is equivalent to the Boolean symbol of •. The event above an AND-gate occurs only when all input events attached to this AND-gate occur simultaneously.
Logic functions for mixed signal circuit design using analog block
Published in Australian Journal of Electrical and Electronics Engineering, 2022
The proposed logic functions using analog building block for modular design of mixed signal systems are verified using the circuitry of Figure 1 biased at ±1.5 V and utilising CMOS 0.25 µm process parameters. The current input signals of rectangular nature are used, and the outputs (for OR and NOR) are obtained as shown in Figure 3. The OR and NOR logic are self-explanatory, with four possible combinations being easily identified in Figure 3. For either/both the inputs at logic 1 (High), the output of OR gate is logic 1, while with both inputs at logic 0 (Low), the OR output is logic 0 (Low). The complement of the above holds true for the NOR outputs, as is clear from Figure 3. The next verification is performed by using capacitive loads of 2 pF each at the gates’ outputs. The waveforms are re-plotted for loaded gates, and the results are shown in Figure 4. The delay for OR gate for high to low transition is found as 250 ns, while for low-to-high the same is 5 ns. These quotes values are measured from the results of Figure 4. The power consumption of the circuit is measures as 2 mW. These performance metrics are to be seen from the usage of an analog design block, rather an optimised digital counterpart, which may exhibit superior figures. Another study performed on the circuit is the effect of load variation, where the capacitive load (CL) is varied from 0.1 to 2.0 pF, and the OR output is plotted as shown in Figure 5. The delay is evidently found to increase as the load capacitor value is increased, as the delay is directly related to the capacitive loads. The verification results for NAND/AND functions are not included for brevity reasons.