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Layout
Published in Michael Pecht, Handbook of Electronic Package Design, 2018
Michael D. Osterman, Michael Pecht
Historically, placement techniques have been developed primarily on the basis of routability. Placement is also based on electrical, thermal, and mechanical guidelines. Electrical guidelines include minimizing the total wire length on the workspace, restricting the maximum length of any routing path, clustering functionally related modules to conform to speed and transmission line requirements, designing signal paths to meet required electrical characteristics (i.e., resistance, current capacity, and capacitances), keeping a strict tolerance on congestion, and keeping analog and digital functions shielded to prevent cross talk. Thermal guidelines include eliminating high thermal gradients on the workspace, placing components in such a way as to allow for adequate spreading of the heat being dissipated, ensuring that all component junction temperatures are kept well within their individual design specifications, and avoiding critical system failures based on the temperature-sensitive failure rates of the individual modules. Vibrational and thermally or mechanically induced stresses that lead to fatigue, cracking, and other related failures must also be avoided. Furthermore, with the demand for high reliability (performance over time), designers have been required to investigate techniques for improving placement based on the reliability characteristics of the board and components. The goal is to improve reliability by decreasing the total failure rate of the system. Overall, the placement configuration should reduce the life cycle cost of manufacturing and maintenance in the field while providing performance over time.
Digital Layout — Placement
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
Placement is an essential step in the physical design flow since it assigns exact locations for various circuit components within the chip’s core area. An inferior placement assignment will not only affect the chip’s performance but might also make it nonmanufacturable by producing excessive wirelength, which is beyond available routing resources. Consequently, a placer must perform the assignment while optimizing a number of objectives to ensure that a circuit meets its performance demands. Typical placement objectives include total wirelength, timing, congestion, and power. In this chapter, we survey the main algorithmic methods used in state-of-the-art placers.
System-on-a-Chip Design and Verification
Published in Nihal Kularatna, Electronic Circuit Design, 2017
Placement arranges the logic cells within the allowed region as guided by the floor plan. Good placement avoids overlap between the cells and makes them easier to wire. In addition, placement should minimize variables such as power dissipation, all performance-critical net delays, crosstalk between signal paths, interconnect congestion, and total interconnect length. Also, blocks must be placed as closely as possible for less silicon area and smaller interconnection delays.
Scheduling of human-robot collaboration in assembly of printed circuit boards: a constraint programming approach
Published in International Journal of Computer Integrated Manufacturing, 2020
Mahdi Mokhtarzadeh, Reza Tavakkoli-Moghaddam, Behdin Vahedi-Nouri, Azadeh Farsi
Printed Circuit Boards (PCBs) assembly includes placement (inserting, mounting) of several electronic components at the specified locations on the board. Typically, a board incorporates a large number of microelectronic components (e.g. resistors and capacitors), that should be placed in their proper place (Crama, van de Klundert, and Spieksma 2002). Some of the related tasks (e.g. checking, testing and manual soldering) can be performed by humans and some of them (e.g. inserting and mounting) can be performed by robots. An automatic PCB workshop includes several machines or workstations that have various features that can perform assemblies (Feo, Bard, and Holland 1995).