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Hardware Description and Synthesis of DSP Systems
Published in Keshab K. Parhi, Takao Nishitani, Digital Signal Processing for Multimedia Systems, 2018
The input to the physical design phase is a circuit diagram and the output is the layout of the circuit. Physical design is accomplished in several stages such as partitioning, floorplanning, placement, routing, and compaction as explained below. Partitioning. – When the design is too large to fit into one chip, the design should be split into small blocks so that each block can be fit into one chip.Floorplanning and placement. – Circuit blocks should be exactly positioned at this stage of physical layout.Routing. – Exactly positioned blocks should be connected to each other at this stage.Compaction. – This is simply the task of compressing the layout in all directions such that the total area is reduced as much as possible.
Overview of Physical Design Issues for 3D-Integrated Circuits
Published in Aida Todri-Sanial, Chuan Seng Tan, Krzysztof Iniewski, Physical Design for 3D Integrated Circuits, 2017
In the recent years, academia and industry have devoted a lot of efforts into understanding the implications and complexity introduced by TSVs. There are novel challenges in all aspects of physical design such as floorplanning, placement and routing, power and clock delivery networks, TSV sizing and distribution, etc. While, 3D integration is becoming a more viable technology for addressing the power wall from aggressive scaling, several physical design solutions already exist to allow exploration of optimal system design for performance, power, and thermal integrity. The rest of this book is dedicated to address each individual’s physical design challenge and provide an in-depth view on the dedicated solutions.
Digital Layout — Placement
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
Placement is an essential step in the physical design flow since it assigns exact locations for various circuit components within the chip’s core area. An inferior placement assignment will not only affect the chip’s performance but might also make it nonmanufacturable by producing excessive wirelength, which is beyond available routing resources. Consequently, a placer must perform the assignment while optimizing a number of objectives to ensure that a circuit meets its performance demands. Typical placement objectives include total wirelength, timing, congestion, and power. In this chapter, we survey the main algorithmic methods used in state-of-the-art placers.
An iterated local search algorithm for solving large-scale instances of the duplex arrangement problem
Published in Engineering Optimization, 2023
MinDA has a great relevance from a practical perspective. One important application of MinDA is related to VLSI physical design. Physical design consists of three main stages: floorplanning, placement and routing (Chang, Chen, and Chen 2006). Assuming there is a set of blocks with fixed shapes, called hard blocks, a set of blocks with shapes to be determined, called soft blocks, and a netlist, in the floorplanning stage the shapes of the soft blocks are established and all the blocks are placed within a rectangular chip area so as to optimize one or more metrics (e.g. wirelength, chip area, wire congestion). In the placement stage, circuit components are allocated a chip region (this can be seen as a floorplanning problem with hard blocks that are similar in dimension) (Chang, Chen, and Chen 2006). Therefore, the placement problem is to assign each rectangular block (circuit blocks or cells) to a position on the chip layout with no overlap between any two blocks (legalization constraint) so as to optimize some objective function (e.g. total wirelength). After placement, the routing stage determines the precise paths used to interconnect all pins that need be connected.