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Design for Manufacturing and Design Process Technology Co-Optimization
Published in Bruce W. Smith, Kazuaki Suzuki, Microlithography, 2020
John Sturtevant, Luigi Capodieci
Prior to sending the GDS file to the mask manufacturing facility, a step called tape-out since the data was initially housed on reels of magnetic tape, it is necessary to verify the design to be manufactured. Design rule checking (DRC) software enables the automatic inspection of a proposed geometric design to confirm compliance with the DRM rules (see Figure 6.3). Additionally, layout versus schematic (LVS) software performs checks that the physical layout structures, when combined together according to rules defined in a so called process technology file, match exactly the original electrical circuit as defined in the gate-level netlist. This will ensure that the desired logical functions will be accomplished by the physical layout. Subsequent extraction (XRC) software enables also the estimate of electrical performance of the manufactured layout. These software tools, as well as the other tools needed earlier in the design flow, are available from multiple EDA vendors, such as Cadence, Synopsys, and Mentor Graphics.
CIRCUIT EQUIVALENCE AND TRANSMISSION LINE THEORY
Published in Wenquan Sui, Time-Domain Computer Analysis of Nonlinear Hybrid Systems, 2018
extend the model complexity to accommodate the additional physical phenomena. For example, as discussed above, the bulk resistor model is under the assumption of uniform current distribution over the cross-section of the conductor, and that model is invalid with skin effect at high frequency. A similar statement can be said about capacitors, inductors, and many other lumped elements for high-speed circuit design. In order to compare a lumped system to its physical representation, which is distributive in nature, Figure 3-11 depicts a simple lumped circuit, a resistor in series with a capacitor, along with its actual physical layout in a semiconductor integrated circuit. Without going into too much detail of circuit layout, the threedimensional structure is briefly described here. The resistor consists of two sections of ion implant, called resistance sheet, which has a measurable resistance per unit length. A resistor with a larger resistance value can be realized by cascading multiple sections of resistance sheets. Common capacitors are made of two parallel plates with dielectric material between them, to increase the unit capacitance. Most semiconductor technology supports multiple layers of metal, along with multiple layers of poly, for power supply, signal routing and ground. Different layers of metal can be connected through via, a small round metal pin connection between layers.
Application-Specific Integrated Circuits
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
M. Michael Vai, William S. Song, Brian M. Tyrrell
Regardless of whether a layout is created manually or automatically, its correctness must be verified. A layout-versus-schematic (LVS) procedure extracts a circuit netlist from the physical layout, which is verified against the original netlist. LVS can be performed with different levels of abstraction. For example, a cell-level LVS considers standard cells as building blocks and extracts a netlist of standard cells by analyzing their physical placement and routing. A mask-level LVS produces from a physical layout a transistor netlist. The user can also select the level of parasitic (resistance, capacitance, and inductance) extraction: no parasitic, lumped elements, or distributed elements. A more detailed extraction gives a more realistic representation of the circuit, but its simulation will be more time-consuming.
A Novel Double-Gate MOSFET Architecture as an Inverter
Published in IETE Journal of Research, 2022
The layout of the proposed DGMOSFET-I and TCAD device cross-sectional view is shown in Figure 9(a,b), respectively. The active layer, source/drain contact, poly, and the substrate are shown in the layout. The design of the physical layout is more linked to the overall performance of the circuit, such as power dissipation, speed, etc. The layout of the inverter presented in the figure shows the MOSFET in n-mode and p-mode. Also, it is highly important to understand the performance parametric values calculated for the proposed device in n-mode and p-mode. Table 2 shows the performance parametric values for p-mode and n-mode at different channel lengths. Figure 10 shows the variation of the transconductance of n-type device vs. gate voltage for different channel lengths. The transconductance is a key parameter used for validating the MOSFET performance in electronic design. The transconductance is the ratio of drain current (Id) to gate–source voltage (Vgs) when a constant drain voltage is applied. Also, the comparison of results obtained on n-type double-gate FET in this work with results published in the literature for the same device is presented in Table 3. The proposed device (this work) exhibits good performance parameters. The best results obtained for the proposed device compared with the literature prompts us use the same device as an inverter incorporated in the same device, which reduces the footprint area.
From behaviour to design: implications for artifact ecologies as shared spaces for design activities
Published in Behaviour & Information Technology, 2020
Christina Vasiliou, Andri Ioannou, Panayiotis Zaphiris
In the following sections we describe the use of different types of digital and physical tools as part of an artifact ecology for collaborative activities. We follow the structure of DiCoT methodological framework; classifying information under the five models: (a) Information Flow, (b) Physical Layout, (c) Artefacts, (d) Social Structures and (e) Evolution over time.