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Design for Manufacturing and Design Process Technology Co-Optimization
Published in Bruce W. Smith, Kazuaki Suzuki, Microlithography, 2020
John Sturtevant, Luigi Capodieci
Prior to sending the GDS file to the mask manufacturing facility, a step called tape-out since the data was initially housed on reels of magnetic tape, it is necessary to verify the design to be manufactured. Design rule checking (DRC) software enables the automatic inspection of a proposed geometric design to confirm compliance with the DRM rules (see Figure 6.3). Additionally, layout versus schematic (LVS) software performs checks that the physical layout structures, when combined together according to rules defined in a so called process technology file, match exactly the original electrical circuit as defined in the gate-level netlist. This will ensure that the desired logical functions will be accomplished by the physical layout. Subsequent extraction (XRC) software enables also the estimate of electrical performance of the manufactured layout. These software tools, as well as the other tools needed earlier in the design flow, are available from multiple EDA vendors, such as Cadence, Synopsys, and Mentor Graphics.
CAD Tools and Design Kits
Published in John D. Cressler, Measurement and Modeling of Silicon Heterestructure Devices, 2018
Design rule requirements are imposed to ensure a variety of quality metrics, including area, timing, power, and yield. Each process step requires mask-layer design for fabrication. Analysis is required on the physical shapes generated by the physical design phase to verify the process steps for manufacturing and tool requirements. Design rule checking (DRC) is a requirement for fabrication and assures manufacturability. Process layers are checked for interaction between layers, metallization vias, overlay tolerances, width and separation limits, shape integrity (Figure 8.6). CAD tools are available to measure physical shapes hierarchically or for flat shapes for specified design rules and report design rule violations to the designer. Some process and design techniques checked in the DRC are discussed in the following sections.
Microelectronic Circuit Enhancements and Design Methodologies to Facilitate Moore’s Law – Part I
Published in Lambrechts Wynand, Sinha Saurabh, Abdallah Jassem, Prinsloo Jaco, Extending Moore’s Law through Advanced Semiconductor Design and Processing Techniques, 2018
Lambrechts Wynand, Sinha Saurabh
To lay out a MOS transistor in a CMOS or bipolar-CMOS (BiCMOS) process, several layers/masks are required to define the structure. The combination of these layers defines the transistor for CAD software to recognize it as a transistor and to perform LVS and post-layout simulations based on the geometries of each layer (Binkley et al. 2003). The DRC defines the minimum and maximum size, overlap and distance among adjacent layers. These layers, which define a transistor, include the n-diffusion, p-diffusion, polysilicon, n-type or p-type well, and metal layers that are isolated from one another by an intermediate oxide (typically SiO2) layer, which is also used to form vias between layers. A layout of a pre-defined NMOS transistor is shown in Figure 7.5 to demonstrate the layer functions of a transistor.
Robust low power transmission gate (TG) based 9T SRAM cell with isolated read and write operation
Published in International Journal of Electronics, 2022
This section gives a brief discussion about the layout of the four of the mentioned and compared SRAM cell configurations. The layouts are made using UMC-130 nm design rules in Cadence. The Virtuoso Layout editor tool is used for the layout. The DRC (Design Rule Check) and LVS (Layout versus Schematic) are performed using the tool, Calibre. The single metallization level (Metal1) is used for interconnections in 6 T SRAM cell. While multiple metallization levels (Metal 1 and Metal 2) is used for 8 T, 9 T and 10 T SRAM cells for making the interconnection in the layout. The different metals are used to have area efficient design. Metal 2 is used for power rails whereas metal1 is for all other connections. The SRAM cells are compared for power, area and delay using post layout simulation results.