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Digital Systems
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
Festus Gail Gray, Wayne D. Grover, Josephine C. Chang, Bing J. Sheu, Roland Priemer, Rung Yao, Flavio Lorenzelli
Figure 9.20 shows a flow diagram for the process typically used to design PLAs and FPGAs. “Design entry” refers to the use of an editor to create a source file that specifies the functional behavior of the device. High-level simulation verifies correct functional behavior of the device. “Logic synthesis” refers to the process of implementing the design using the primitive elements present on a specific chip, such as gates, flip-flops, registers, etc. Most development systems support prelayout simulation at this level to verify that the design still functions correctly. “System partitioning” and “mapping” refers to the process of grouping blocks of primitive elements into sets that map directly into major chip structures, such as CLBs in FPGAs or AND–OR arrays in PLDs. “Place and route” refers to mapping the structures into specific locations on the chip and making connections between them. The software package then performs a timing analysis on the final design to verify that design timing specifications are met. Finally, the chip is configured by generating an output file that can be read by the chip programmer.
A Review on SEU Mitigation Techniques for FPGA Configuration Memory
Published in IETE Technical Review, 2018
T. S. Nidhin, Anindya Bhattacharyya, R. P. Behera, T. Jayanthi
Routing fabric becomes more important in the FPGA architectures even after the advancement in the technologies [56]. The programmable routing in an FPGA can be categorised as routing within each logic block and routing between the logic blocks. Interconnect matrix is the routing structure within the logic blocks and switch blocks define the routing structure between the logic blocks. The interconnections are carried out through programmable switches; it consists of a pass transistor controlled by a static RAM cell [57]. A detailed routing architecture is depicted in Figure 4. The routing resources constitute most of the configuration bits, almost 90% of the configuration bits are for routing resources. A reliability-oriented place and route algorithm (RoRA) which first performs a reliability-oriented placement of each logic blocks belonging to the implemented design; second, it routes the signals between the logic blocks in such a way that multiple errors affecting two different connections are not possible [58].
A Review on HT Attacks in PLD and ASIC Designs with Potential Defence Solutions
Published in IETE Technical Review, 2018
G. Sumathi, L. Srivani, D. Thirugnana Murthy, K. Madhusoodanan, S.A.V. Satya Murty
With the increasing globalisation trend, most of PLD vendors become fabless suppliers and outsource the design for manufacture, e.g. Xilinx uses Taiwan Semiconductor Manufacturing Corporation. From chip vendors, the system designers procure the devices. Later, following a set of design procedures with the aid of IP cores and EDA tools, designers program the device. Finally, the system with programmed devices is deployed into the environment. Eventually, the life cycle of any PLD has a constant deal with multiple third-party accesses such as vendors during chip design and trade, foundry during manufacture, customers during configuration, and field exposure during operation. To categorise potential HTs allied with various stages of PLDs, we classified the life cycle of PLDs as (i) Pre-customisation phase, (ii) Customisation phase, and (iii) Post-customisation phase as shown in Figure 1. Pre-customisation phase deals with the blank i.e., unprogrammed devices, which includes design (i.e. vendor) and manufacturing (i.e. foundry) stages. Next phase is the customisation phase, where the PLD is integrated into the final system and is programmed to implement its intended functionality. To explain in detail about customisation phase, it starts from coding the design using hardware description language (HDL), synthesis (netlist generation), simulation, mapping to technology-specific components, place and route (PAR), generation of the configuration bitstream, and finally programming the target device. Based on the application, the programmed device is assembled with few other functional blocks such as digital signal processing (DSP), analogue-to-digital converter (ADC), digital-to-analogue converter (DAC), memory, etc. and deployed in the field. This field operating condition and associated access come under post-customisation phase.