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Floating-Point Computations with Very-High-Speed Integrated Circuit Hardware Description Language and Xilinx System Generator (SysGen) Tools
Published in A. Arockia Bazil Raj, FPGA-Based Embedded System Developer's Guide, 2018
Channel Decimate by 2 MAC FIR Filter: The Xilinx n-tap 2 Channel Decimate by 2 MAC FIR Filter reference block implements a multiply-accumulate-based FIR filter. One dedicated multiplier and one Dual Port Block RAM are used in the n-tap filter. The same MAC engine is used to process both channels that are TDMed together. Completely different coefficient sets can be specified for each channel as long as they have the same number of coefficients. The filter also provides a fixed decimation by 2 using a polyphase filter technique. The filter configuration helps illustrate techniques for storing multiple coefficient sets and data samples in filter design. The Virtex FPGA family (and Virtex family derivatives) provide dedicated circuitry for building fast, compact adders, multipliers and flexible memory architectures. The filter design takes advantage of these silicon features by implementing a design that is compact and resource efficient. Implementation details are provided in the filter design subsystems.
System-Level Organization of the FCR
Published in Lev Kirischian, Reconfigurable Computing Systems Engineering, 2017
For example, if Xilinx Spartan 3S (XC3S400-4FGG456) is used as an interconnect switch (router), it can provide 264 I/O pins or 4 × 64-bit I/O ports plus 2 extra pins for control/synchronization signals per port. The cost of this additional onboard communication FPGA-based switch is approximately $40. It is necessary to mention that in most cases the reason for the expansion of the FCR from single to multiple FPGAs is the lack of logic on-chip resources in the single FPGA. Thus, each FPGA is assumed as the largest device in its family. However, large Xilinx FPGA devices are relatively expensive units. For example, the cost of Xilinx Virtex-6 FPGA XC6VLX240T-1FF784C with 400 I/O pins is close to or more than $2000. Therefore, the overhead cost of additional $10/port is negligible in comparison with the cost of the large FPGA of the same vendor.
Computing Devices
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
Developed initially for implementing digital logic functions, FPGAs have become extremely capable computing engines thanks to Moore’s Law scaling of device parameters. Xilinx Virtex FPGAs, for example, are SRAM-based devices consisting of a sea of programmable logic cells called slices made up of 4-input look-up tables (LUTs) and registers arranged in grid fashion and interconnected by a programmable interconnect. Newer Virtex FPGAs also include memory blocks and DSP blocks, which include dedicated multipliers and adders, as part of the basic fabric. Serial I/O blocks and in some cases (Virtex-II, Virtex-II Pro) PowerPC cores are also included. Table 13-3 shows how the capability of the Virtex FPGA has evolved over time with decreasing feature sizes. In the newer devices with dedicated multiplier and DSP blocks, hundreds of arithmetic operations can be executed on each clock cycle, yielding hundreds of GOPS per device. Floating-point arithmetic can also be implemented by using multiple blocks per floating-point operation, with additional logic slices used for rounding and normalization. It is, of course, up to the FPGA designer how to implement processing functions using the basic building blocks provided, and here, despite recent advances in design tools, the process is still much more like hardware design than software programming and can be quite labor intensive. On the plus side, it is also possible to carefully optimize specific designs, resulting in very high performance, highly efficient designs that use a significantly greater fraction of the available resources than is possible with a general-purpose programmable processor.
Design and Implementation of Enhanced PUF Architecture onFPGA
Published in International Journal of Electronics Letters, 2022
Remember that PUF must be a symmetrical circuit. Otherwise, signals passing through the two path takes increase in time to reach output. In Xilinx ISE software, the circuit components are placed according to its place and routing algorithm. Such situation is not desirable because when new module is added to the project, changes the placement of the components which lose the symmetrical path between the circuit. In order to get a symmetrical placement, relative locationing is used, so that the placement of the circuit components are fixed at a particular location in the FPGA. The Proposed DFFX APUF is implemented on Virtex- 6 using Xilinx ISE 14.7 under normal room temperature. In order to compare the results of proposed DFFX-APUF with existing DAPUF and FF-APUF, are implemented on 2 vietex-6 board with 5 (5X2) different locations on each FPGA board, which means that placing the PUF circuit at 10 different locations by fixing the positions on the FPGA as shown in Figure 9. To make the design unbiased, the manual placement is done while mapping into FPGAs. To achieve the accurate result, combination of input challenges are more in number. In this work, 5000 combination of 64-bit Challenge as input and observing the corresponding 64-bit response (R) as output. 64-bit, 5000 random combination data is stored in the SRAM and then applied to the main PUF design. To maintain the challenge length as N, consider the N + M is the total length of MUX chain, where M is Feed-Forward path.
An Efficient FPGA Realization of Seizure Detection from EEG Signal Using Wavelet Transform and Statistical Features
Published in IETE Journal of Research, 2020
An efficient seizure detector from EEG signal using wavelet transform and statistical features was realized in FPGA. It can replace the traditional visual inspection method of EEG for seizure detection. A new hardware efficient multiplierless architecture of 3/5 B-Spline wavelet is used for subband decomposition and verified the same. Derived statistical features variance, standard deviation, mean energy, skewness, kurtosis, and the feature maximum amplitude from the selected subband. Analysis of features shows a significant difference in the feature values derived from the EEG signal of epileptic seizure affected and not affected. In seizure affected EEG database, the values are statistically dispersed more and the imbalance or asymmetry is high. Trained and tested the detector system successfully in MATLAB and FPGA platform using SVM classifier. The system is verified by Verilog in ISim simulator and synthesized in Virtex 6.
Hardware-in-the-Loop simulation algorithm for helicopter rotor time-varying echo signals
Published in Systems Science & Control Engineering, 2021
According to the real-time simulation algorithm and the error analysis in Section 4.1, the simulation algorithm only needs basic calculations and trigonometric functions to simulate additional helicopter rotor echoes in real time. Because we calculate the echo data of each helicopter rotor (real signal), the number of operations required for multiplication is approximately three, and the number of operations for addition is approximately one. If the working frequency of the multiplier is 250 MHz, for a data rate of 500 MHz, we only need approximately six DSP units to realize the real-time calculations. As stated in Section 1, the real-time analysis is mainly evaluated through the DSP resources consumed by the system. As this study uses a Xilinx's Virtex-7 series field programmable gate array (FPGA), X7CVX415T-1FFG1157C, the number of DSP units in the chip can reach a maximum of 2,160. This implies that the DSP resources required by the proposed algorithm account for approximately 0.28% of those in Xilinx's Virtex-7 series FPGA, which is a considerably low percentage. Therefore, the proposed algorithm can be used in real time. Moreover, when engineers design a helicopter rotor blade, they need to analyse multiple aspects, such as dynamics, rotor rotation speed, and the severity of the resonance phenomenon of the rotor. Severe resonance causes significant vibrations and noise problems in the rotor system. This will have a strong impact on the helicopter’s flight performance, stability, and manoeuvrability (Yang et al., 2014). Furthermore, once the helicopter's rotor is designed, its related parameters (N, σ, frot, and l) are determined.