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Hardware Based Data Compression using Lempel-Ziv-Welch Algorithm
Published in Durgesh Kumar Mishra, Nilanjan Dey, Bharat Singh Deora, Amit Joshi, ICT for Competitive Strategies, 2020
Onkar Choudhari, Marisha Chopade, Sourabh Chopde, Vaishali Ingle
In the proposed work, simulation results are produced using Xilinx ISE simulator. The proposed technique results in reduced storage space to 66.66 %. Figure 2.4 is the block RAM memory loaded with input file. The input text Shreeram ram raghunandana ram ram, Shreeram ram bharatagraja ram ram. Shreeram ram rankarkasha ram ram, Shreeram ram sharnam bhav ram ram.# is of 1112 bytes with each character 8 bits long. Figure 2.6 is the output block RAM memory having codes replacing string. The output file size is 740 bytes with each code 10 bits long. Thus a compression ratio of 1.5 is achieved.
A Novel Energy-Efficient MIMO-OFDM Decoder Architecture with Error Detection
Published in IETE Journal of Research, 2023
The proposed hybrid classifier and VLSI-based decoder architecture contribute to the energy-efficient transceiver section. The results, simulated from Xilinx ISE 14.2, ModelSim 10.0b and Cadence, under 90 nm technology have shown the system performance with an accuracy and sensitivity of 86.4% and 91.1%, respectively. The merits of the system are reduction in the parameters such as less area of 13.21 × 102 and average power of 4.35 × 102 mW along with the throughput calculated by fetus signal received per second at output is determined to be 90.02%. Overall error rate of the system for measuring accuracy of noise hit is determined from mean of successful runs to total number of runs and is estimated to be 93.7%. Hence optimum results are achieved with the architecture for the extended range of data [n ≤ 256] with neither deviation nor misinterpretation in the detected fetal signal at receiver.
Development and design of an FPGA-based encoder for NPN
Published in Cogent Engineering, 2022
M.K. Ibraimov, S.T. Tynymbayev, A.A. Skabylov, Y. Kozhagulov, D.M. Zhexebay
The data encryption and decryption algorithm was designed and tested in the Xilinx ISE Design Suite 14.4 computer-aided design (CAD) and the hardware description language (HDL) Verilog was used. Some blocks and subblocks were written in VHDL. The multiplication of polynomials modulo irreducible polynomials was applied in this work, where multiplication is done with the analysis of lowest bits of multiplier.
Implementation of PSO algorithm for MIMO detection system in FPGA
Published in International Journal of Electronics, 2018
Abdessalem Trimeche, Anis Sakly, Abdellatif Mtibaa
We use MATLAB, Xilinx ISE, XSG and ModelSim. The results have been simulated from the data given in the database and corrupted with reliable noises with the ones encountered in the real test bench (Tewolde, Hanna, & Haskell, 2009). Figure 13 shows the general model design of equaliser used in Simulink.