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Digital Systems
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
Festus Gail Gray, Wayne D. Grover, Josephine C. Chang, Bing J. Sheu, Roland Priemer, Rung Yao, Flavio Lorenzelli
Figure 9.20 shows a flow diagram for the process typically used to design PLAs and FPGAs. “Design entry” refers to the use of an editor to create a source file that specifies the functional behavior of the device. High-level simulation verifies correct functional behavior of the device. “Logic synthesis” refers to the process of implementing the design using the primitive elements present on a specific chip, such as gates, flip-flops, registers, etc. Most development systems support prelayout simulation at this level to verify that the design still functions correctly. “System partitioning” and “mapping” refers to the process of grouping blocks of primitive elements into sets that map directly into major chip structures, such as CLBs in FPGAs or AND–OR arrays in PLDs. “Place and route” refers to mapping the structures into specific locations on the chip and making connections between them. The software package then performs a timing analysis on the final design to verify that design timing specifications are met. Finally, the chip is configured by generating an output file that can be read by the chip programmer.
Congestion-Driven Physical Design
Published in Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 2008
Saurabh N. Adya, Xiaojian Yang
The work by Pandini et al. [31] proposes several techniques to incorporate congestion minimization within logic synthesis. Modern logic synthesis systems are typically divided into two phases: technology-independent optimization and technology mapping. The first phase is concerned with finding a representation of the Boolean equations with the minimum number of literals in the factored form. Technology mapping is the task of transforming a technology-independent logic network into a technology-dependent gate-level netlist. A popular approach to technology mapping implemented in DAGON [12] and MIS [24] is to reduce the problem to directed acyclic graph (DAG) covering problem. The DAG covering problem was approximated by a sequence of tree coverings, which can be solved optimally using dynamic programming. The technology mapping is usually divided into three stages: DAG partitioning, matching, and covering. During DAG partitioning, the network DAG is partitioned into a forest of trees. Subsequently, for each tree, a matching algorithm identifies all possible matches, corresponding to instances of a cell library, for each subnetwork. Finally, an optimal choice according to a cost factor is selected among the matches. The work in Ref. [31] targets the DAG partitioning and covers steps to improve congestion of the final implementation.
Design Closure
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
Because of the relative ease of running logic synthesis with different optimization targets, designers use it to explore the design space and make the best performance, power, and area trade-offs for their design. In order to achieve the area, power, and performance goals, logic synthesis applies a number of techniques to the technology-mapped netlist. In order to do this, these factors need to be measured: logic area is measured by adding up the sizes of the various gates; power is assumed to be a function of gate size — reducing gate sizes reduces power. Measuring performance is more complicated, and the logic synthesis is the first phase to rely heavily on static timing analysis. Since the placement of the dust logic has yet to be defined, wire-load models, usually a function of fanout, chip size, and technology, are used to estimate parasitic effects. There are subtle interactions between the wire-load-based parasitic estimation of the logic synthesis phase and subsequent placement and logic/placement refinement phases. If the wire-load models overestimate loading, then the power levels in the gates in the resulting design passed to placement will be excessively large, with no real way to recover the over-design. However, if the parasitic estimation is optimistic, then optimization in this phase will not focus on the correct problems. In general, erring on the side of optimism produces better results, especially with the advent of truly effective timing driven placement flows, to the point that many chips are now synthesized with zero-wire-load models for local signals, and load estimates for global signals derived from the floorplanning step. Since the clock distribution circuitry has yet to be added, idealized clock arrival times are applied to launch and capture clocks at latches. This step must also anticipate the impact of buffer insertion that will be performed during and after placement to prevent interconnect delay from being over estimated.
Ideas for Improving the Digital Design Lab
Published in IETE Journal of Education, 2023
A student may be required to build an up/down counter, a modulo-m counter or a sequence generator as part of a lab experiment. The objectives of such an experiment are as follows. To understand the operation of different types of counters and be able to design a synchronous counter from scratchTo understand why synchronous counters are preferred over asynchronous countersTo understand the process of designing a counter using JK, D, or T flips. This includes finding the excitation tables for J, K, D, or T inputs for each flip-flop and find a minimal product-of-sum expression for each excitation logic.To verify the correctness of the design through simulation There are numerous ways to approach this experiment. One way is to do a paper-and-pencil design and then build the circuit using available flip-flops and logic gates. There is a risk of making an error in the design or in rigging up the circuit. Given that the experiment must be completed in about 3–4 hours, the lab instructor may have to ask the student to come with the design to the class. The students can get the correct design from the instructor and verify the correctness of their own design. In many colleges, the students are given a lab manual where the design is provided. There are also “kits” where a counter design has already been implemented a priori and the student is only required to rig up the circuit and verify its operation. We feel that an intermediate solution, where the student can be assisted with some automation tools for design, may reduce the effort without occluding the learning. While it is possible to use logic synthesis tools and logic simulation tools with test-benches written in a hardware description language, there are two challenges in using HDL – (a) availability of HDL synthesis and simulation tools is not guaranteed, (b) there is a steep learning curve associated with HDL tools. Often, a student may have to spend many hours learning to use the tools. Many colleges overcome this problem by providing a step-by-step procedure to perform the experiment, along with the required files. This approach does not allow the student to assimilate the skills.