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Introduction
Published in David Cavalheiro, Francesc Moll, Stanimir Valtchev, Ultra-Low Input Power Conversion Circuits based on Tunnel-FETs, 2022
David Cavalheiro, Francesc Moll, Stanimir Valtchev
Since 1947, with the invention of the first transistor by William Shockley, John Bardeen, and Walter Brattain at Bell Labs [1] and the Integrated Circuit (IC) at Texas Instruments by Jack Kilby in 1958 [2], the impact of the evolution of electronic technology in our daily activities has been so enormous that nowadays it is unthinkable to live without it. Smart cars, smart phones, smart watches, smart TVs, and healthcare gadgets are just a few examples of technology that eases our daily life, mainly due to the downscale evolution of the electronic transistor. The exponential growth of the transistor count on a die, following Moore’s law [3] has been the major impulse for the semiconductor industry over the years. The decrease of the technology node and the consequent transistor channel length has led to the possibility of adding more devices on a single die, thus reducing the production cost of a chip and increasing its complexity. Also, the reduction of the transistor size allowed the design of faster circuits with reduced power consumption (per transistor).
Introduction to Voice-Activated Assistants
Published in Jeff J. H. Kim, Richard Um, Rajiv Iyer, Nicholas Theodore, Amir Manbachi, Design and Development of Smart Surgical Assistant Technologies, 2022
Jeff J. H. Kim, Richard Um, Rajiv Iyer, Nicholas Theodore, Amir Manbachi
The significant expansion of the internet and advanced microprocessor technology has enabled the rise of next-generation voice-activated assistants. Advancement in the microprocessor space enabled an exponential increase in processing power due to the rapid rise of transistor count.8 As mentioned previously, the root of this phenomenon was the rise of system-on-chip circuits, also known as IC. Instead of utilizing motherboard-based PC architecture, which separates components based on functionality, integrated circuits allowed the consolidation of main and peripheral processing cores in a compact form. This had two main benefits that ultimately laid the groundwork for IoT technology.9 The first is the significant reduction of size and vast improvement in computing and battery performance. Second, the rise of the modern internet and short-range wireless technology demonstrated the value of IoT technology, as access to the internet and device interconnectivity expanded the scope of voice-activated smart assistant capabilities. Short-range wireless technology such as Bluetooth advanced inter-device communication, while faster data transfer protocol expanded the scope of control over sensors and actuators.10 This, in simple terms, gave arms and legs to the brain of the system, thereby facilitating smart functions such as controlling a thermostat with a smart home device. These two developments naturally gave rise to the highly capable and compact voice-activated smart assistant devices we know and love today (Figure 1.3).
Semiconductor Memory Technologies Overview
Published in Shimeng Yu, Semiconductor Memory Devices and Circuits, 2022
It was predicted by Dr. Gordon Moore, Intel’s co-founder, in the late 1960s, that the transistor count on a processor chip (or a die) would exponentially grow (i.e., double approximately every 2 years. This prediction is referred to as the famous Moore’s law [6], and it has become the driving force for the technology scaling in the semiconductor industry over the past 5 decades. From generation to generation, the effective area per transistor is supposed to shrink by ~0.5×, which is translated to a dimensional scaling by ~0.7× (the square root of 0.5×). It should be noted that Moore’s law is not a physical law that defines the transistor’s dimension must be downscaled by 0.7×, but rather is an economic law that aims to lower the cost per transistor. At the same time, better performance or more chip functionalities are obtained as a byproduct of the scaling. Figure 1.11 plots the transistor count on the die for a variety of microprocessors (including Intel’s personal computer/server CPUs, Apple’s mobile CPUs, and Nvidia’s GPUs), as well as DRAM and NAND Flash. A few observations could be made from this chart. First, the microprocessors today generally contain more than a billion transistors on the die (and a big portion of these transistors are used to build SRAM). Second, the transistor count of standalone memories (DRAM and Flash) on a die outpaces that of the microprocessors in the recent decade. The NAND Flash (especially the 3D version of it) is the technology that has the highest integration density, approaching a trillion of transistors on the die.
Implementation of Novel Block and Convolutional Encoding Circuit Using FS-GDI
Published in IETE Journal of Research, 2023
Mohsen A. M. El-Bendary, O. Al-Badry, A. E. Abou-El. Azm
The presented approach for implementing the various encoding circuits using FS-GDI logic style improved the power efficiency and speed of FEC schemes compared to the traditional approach, as cleared and listed in Table 5. The presented Hamming encoding circuit achieved an improvement in power consumption by 30.9%, while the convolutional encoding improved by 44.0% in power efficiency. The speed efficiency of the proposed encoding circuits has been improved by about 27.0%–30.7%. On the other hand, the hardware complexity as represented by the transistor count improved in the presented FS-GDI-based encoding circuits. The hardware complexity is measured by the transistor count of the implemented circuits. Hence, the utilized XOR based on FS-GDI requires 6 Ts, while using the traditional CMOS approach requires 12 Ts. Therefore, the H/W complexity is reduced by 50%.
A 4:1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology
Published in International Journal of Electronics, 2020
Sandeep Garg, Tarun K. Gupta, Amit K. Pandey
Dynamic CMOS logic circuit represents lower threshold voltage, logical effort and parasitic capacitance compared to static CMOS logic circuits. Therefore, dynamic circuits operate faster and occupy lesser area on chip in contrast to static circuits. For implementing large Fan-in gates, dynamic logic is preferred over static logic in high-speed digital applications. The transistor count on chip is increasing due to technology scaling. This increase in chip density causes more number of interconnects on the chip that increases the capacitive coupling between the interconnects. This coupling causes crosstalk between the interconnects due to noise pulses and reduces the speed of the domino circuit. The supply voltage (VDD) is scaled down for reduction in power consumption of domino circuits. Threshold voltage (Vth) of the transistors is reduced along with the decrease in supply voltage to maintain the power and delay performance of transistors. This increases the sub-threshold current that will make the circuit faster and reduces noise immunity. In addition, due to technology scaling, the thickness of gate oxide decreases which increases gate leakage current. Therefore, at high frequencies, the performance of domino logic is degraded due to leakage current, low Vth and noise sources (Anis, Areibi, & Elmasry, 2003; Dadashi, Mirmotahari, & Berg, 2016; Roy, Mukhopadhyay, & Mahmoodi, 2003).
A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process
Published in International Journal of Electronics Letters, 2023
Chua-Chin Wang, Lean Karlo S. Tolentino, Uday Kiran Naidu Ekkurthi, Pang-Yen Lou, Sivaperumal Sampath
By eliminating the negated input trigger and the subsequent devices, MN12 and MP12, the proposed DETFF architecture in Figure 5 is improved. The flip-flop’s functionality is not only affected by these added devices. The transistor count is also reduced; thus, resulting in a lower area of the core, lower cost, and lower power dissipation.