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Process Variability and Reliability of Nano-Scale CMOS Analog Circuits
Published in Soumya Pandit, Chittaranjan Mandal, Amit Patra, Nano-Scale CMOS Analog Circuits, 2018
Soumya Pandit, Chittaranjan Mandal, Amit Patra
As the semiconductor process technology scales into nanometer dimension, the printability and process window of the finer lithographic patterns are significantly reduced due to the fundamental limit of the microlithography systems. As for now, leading IC fabs still use the 193nm lithography systems to print sub-wavelength feature size (e.g., 65nm or even 45nm), with the aid of various sophisticated resolution enhancement techniques (RET), such as optical proximity correction (OPC), phase shift mask (PSM), etc. [31]. However, the complex steps of these lithographic techniques increase the risk of process variations even further. These process variations are found to be systematic in nature. Apart from the RETs, layout induced strain, well-proximity effect, etc., are some other sources of systematic process variations. The systematic sources of process variation can be mitigated either by more controlled RETs or can be modeled and subsequently incorporated in the design. This section introduces some major sources of systematic process variations.
Implementing Solutions
Published in James William Martin, Lean Six Sigma for the Office, 2021
There are other control tools that are effective for maintaining process performance. An example is Statistical Process Control (SPC), which uses different types of control chart to detect excess process variation of key variables documented in the control plan. Statistical Process Control will now be discussed in detail becomes it has several important attributes relevant for effective control.
Statistical Process and Quality Control
Published in William M. Mendenhall, Terry L. Sincich, Statistics for Engineering and the Sciences, 2016
William M. Mendenhall, Terry L. Sincich
All three components of Figure 16.1 are necessary to successfully implement a TQM methodology at a company. In this chapter, we focus on the statistical process control element of TQM. Statistical process control (SPC) allows engineers to understand and monitor process variation through control charts.
Design and analysis of MISO bi-quad active filter
Published in International Journal of Electronics, 2019
Vikash Kumar, Rishab Mehra, Aminul Islam
The impact of process variation is analysed through Monte Carlo simulations which approximate the statistical variations in the filter characteristics corresponding to the variations in process parameters. The process parameters such as W, L, tox and NCH are assumed to have independent Gaussian distributions with a 3σ variation of ± 10% as projected by the International Technology Roadmap for Semiconductor Industry (ITRS) guidelines (ITRS, 2009). The Monte Carlo sample size was taken to be 2000 samples. The distribution plot for the pole frequency (ωp) of the active band-pass filter is shown in Figure 14. The standard deviation (σ) of 395.144 KHz around the mean (µ) of 1.3178 GHz results into a variability (σ/µ) of 299.85 × 10−6.
Shewhart dispersion charts made easy for mild to moderately autocorrelated normally distributed data
Published in Quality Engineering, 2018
Statistical Process Control (SPC) has been incorporated by many organizations around the world as a primary tool to reduce process variation and improve product quality. A key component of SPC methodology is the control chart used to distinguish between process variations that can be attributed to common (non-assignable) causes and those that indicate special (assignable) causes. Detecting and removing special causes of variation is the key to quality improvement. The most commonly used control charts are those pioneered by Walter A. Shewhart in the 1920s. While initial applications were primarily in manufacturing processes, the practical applications of control charts nowadays extend into fields as diverse as disease surveillance (e.g., Sparks et al. 2010), monitoring institutional performance (e.g., Speigelhalter, 2002), monitoring of the environment and monitoring services (Strauss, 1978).
DPL-based novel time equalized CMOS ternary-to-binary converter
Published in International Journal of Electronics, 2020
The PVT (Process-Voltage-Temperature) variation introduces detrimental effect on the reliability of VLSI circuits and systems. The result is more apparent when time-equalisation is an important design requirement. Process variation occurs due to several practical issues related to chip fabrication as well as wafer processing (Saha & Pal, 2018), (Saha et al., 2013), and (Weste & Harris, 2011). Process variation may cause a particular device to work faster or slower than its nominal rate due to uncontrolled variation in device dimension, doping, threshold voltage etc. (Saha et al., 2013). On the other hand supply voltage and temperature variation also contribute to overall performance of time-equalised circuits. Voltage variation may occur due to source regulation, voltage-drop (because of path resistance), di/dt effect and the like (Weste & Harris, 2011) whereas temperature depends on various ambient conditions and also on the heat generated inside the IC. As per industry standard the IC should be reliable within supply range of ±10% of its nominal value and also for temperature variation over −40 to 85°C (Saha & Pal, 2018), (Saha et al., 2017), and (Weste & Harris, 2011). In case of time-equalised circuits the collective effect of PVT variation may increase output delay dispersion and hence can degrade overall speed performance significantly (Saha & Pal, 2018). Again delay variation at intermediate stages due to PVT variation may create spurious transitions that in turn can make the circuit need more power. The overall result may lead to circuit mal-functioning or unreliable operation. Thus, reliability-estimation of proposed TBC design for possible PVT variations becomes an essential part in the present work.