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Advanced Power Management Methodology for SoCs Using UPF
Published in Durgesh Nandan, Basant K. Mohanty, Sanjeev Kumar, Rajeev Kumar Arya, VLSI Architecture for Signal, Speech, and Image Processing, 2023
Usha Rani Nelakuditi, Naveen Kumar Challa, Kurra Anil Kumar
The emergence of new generation technologies with small threshold voltage devices causes the leakage power with increased static power dissipation [3]. To realize high performance chips, lower threshold voltage devices are preferred, but they are responsible to the increase of leakage power. At lower technologies like 65 nm [5] leakage power is a major concern in addition to the dynamic power. Hence supply voltage scaling is an important power management technique used to control the leakage and dynamic power components. Hence at present people are putting efforts on developing methods with voltage as a design parameter. Power reduction techniques such as multi-voltage, power gating, clock gating, dynamic voltage, and frequency scaling and management techniques are based on scaling and also power distribution network across the chip. In case of SoCs, power reduction methods are not sufficient, hence power verification methods are also necessary can be introduced at any abstraction level such as transistor, gate, or RTL.
Gate and Channel Engineered Nanoscale Electronic Devices
Published in Khurshed Ahmad Shah, Farooq Ahmad Khanday, Nanoscale Electronic Devices and Their Applications, 2020
Khurshed Ahmad Shah, Farooq Ahmad Khanday
In logic applications, the MOSFET is used as a switch, which ideally has zero ON resistance and infinite OFF resistance. Ideally, a switch turns ON if the applied voltage is greater than 0 V but, in case of MOSFET, the ON state is decided by the threshold voltage. If the applied gate source voltage (VGS) is greater than threshold voltage (VTH), the MOSFET turns in ON state and conducts current. The MOSFET remains in the OFF state and does not conduct the current if the applied VGS is less than the VTH. Thus, the threshold voltage plays a critical role in circuit operation, and it is also a very important design parameter for MOSFET due to its dependence on doping in the silicon body, on the depleted charge in the channel due to gate voltage, on the trapped charge at the silicon–silicon dioxide interface and on the gate material [22]. In small geometry MOSFET, part of channel depletion charges is influenced by the presence of source and drain diffusion regions. For sub-100 nm MOSFET, the charge associated with p–n junctions becomes relatively large part of the depletion charge (present in the small channel), and the gate control over the channel electrostatics is reduced. The control is further reduced as the drain–source voltage (VDS) is increased. Thus, in the design of a nanoscale MOSFET, the threshold voltage sensitivity to channel length and drain voltage is a crucial issue.
Analytical Modeling of High Electron Mobility Transistors
Published in D. Nirmal, J. Ajayan, Handbook for III-V High Electron Mobility Transistor Technologies, 2019
Drain-induced barrier lowering (DIBL) is the most prevalent short-channel effect. The concept of DIBL effect is described by the channel potential where the sub-threshold leakage current often occurs at the minimum channel potential. The device threshold voltage plays a major role in the control of DIBL effect. The threshold voltage is the minimum potential required to turn on the device. Here gives a measure of drain induced barrier lowering. Hence the position of minimum channel potential is evaluated by setting, () dϕl(x)dx=0
Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS Technology
Published in IETE Journal of Research, 2023
To achieve higher performance of the CMOS device circuit along with high densities, there have been reductions in supply voltages, device dimensions and transistor threshold voltages over the years. But, these reductions have also resulted in higher leakage currents that can severely affect power consumption in a circuit. The power consumption of any CMOS VLSI circuit is composed of dynamic power and static power. The dynamic power dissipation is due to the switching activities of the circuit while the static power dissipation occurs due to the leakage components of the circuit during the standby mode. During submicron technology when the feature size was greater than 350 nm, the leakage power dissipation was smaller than dynamic power by several orders of magnitude [1]. With technology scaling there is a need of lowering of supply voltage and threshold voltage of VLSI circuits. However lowering of threshold voltage increases the static power dissipation. In ultra-deep submicron technology where the feature size is lesser than 100 nm, static power dissipation has dominated the dynamic power. Thus there is need for reducing the static power dissipation in ultra-deep submicron technology.
Waveform analysis of carbon nanotube interconnects connected to various driver/load circuits
Published in International Journal of Electronics, 2021
P. Uma Sathyakam, Ananyo Banerjee, P. S. Mallick
The subthreshold operation of transistors and interconnects is one of the basic requirements of future nanoelectronic circuits (Jamal & Naeemi, 2011). As the device dimensions shrink, the voltage required to drive them also reduces. When the devices operate at voltages below the threshold voltage, the power dissipated by them reduces substantially. This is preferable for low power circuits as well as portable electronic devices. However, one of the main bottlenecks in implementing subthreshold circuits is their inherent low speed of switching signals from high to low and vice versa, compared to circuits that operate at nominal or superthreshold voltages (Jamal & Naeemi, 2011). This is mainly due to the fact that the subthreshold current is very small compared to superthreshold current in the circuit. This small current may not be sufficient to drive the signal from low to high (0 to Vdd) and vice versa. Hence, mechanisms like transistor sizing by varying its channel length and designing of driver/load circuits for interconnects can increase the subthreshold current.
A comparative study on the self-heating effect of ion-implanted MESFETs
Published in International Journal of Electronics Letters, 2021
The variations of the threshold voltage of the MESFET based on GaAs, GaN, and SiC with device temperature are presented in Figure 5. It is observed from the figure that threshold voltage increases with temperature in general. The MESFET based on GaAs offers largest threshold voltage and for GaN device the threshold voltage is observed to be minimum. Such nature of variation can be explained as follows. From Figures 3 and 4, it is observed that GaN MESFETs offer maximum and GaAs MESFETs offer minimum current value. So a comparatively large reverse gate bias is required to achieve threshold condition of the device. That is why threshold voltage is minimum for GaN MESFET and maximum for GaAs MESFET. The enhancement of threshold voltage with temperature follows the reduction of drain current with temperature.