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Modeling Process Variability in Scaled MOSFETs
Published in Samar K. Saha, Compact Models for Integrated Circuit Design, 2018
Systematic variation in IC (integrated circuit) device and chip performance is caused by inherent random character of IC-processing steps. The systematic component is defined as the global or inter-die process variability [1,9–13]. The global process variability causes die-to-die, wafer-to-wafer, or lot-tolot systematic parametric fluctuations between identical devices [1,9–13]. Global variability causes a shift in the mean value of the sensitive design parameters, including the channel length (L), channel width (W), gate oxide thickness (Tox), resistivity, doping concentration, and body effect as shown in Figure 8.2. Systematic differences may lead to longer channel length transistors than the nominal devices, causing them to switch more slowly due to reduced drive current, resulting in slower ICs with lower leakage current. On the other hand, the shorter (than the nominal) channel length devices would lead to faster die easily meeting clock-frequency specifications; however, these devices may exhibit excessive leakage current and fail leakagecurrent specifications. In the semiconductor industry, the systematic process variation has been the major interest to IC chip manufacturers in maintaining competitive yield over multiple technology nodes [4]. The systematic process variability in manufacturing technology has been accounted in compact modeling by defining process corners, that is, boundaries in parameter variation that account for process tolerances [1,9].
Process Variability and Reliability of Nano-Scale CMOS Analog Circuits
Published in Soumya Pandit, Chittaranjan Mandal, Amit Patra, Nano-Scale CMOS Analog Circuits, 2018
Soumya Pandit, Chittaranjan Mandal, Amit Patra
Worst case analysis basically consists of considering the results of the worst combinations of the extreme fluctuations in an IC process in order to evaluate the range of circuit performance variations. The worst case corner models are generated by setting each process sensitive compact model parameters at a value deviated from their corresponding nominal values by some fraction of their respective standard deviations. In the case of MOSFETs, nominal values are captured in what is known as a ‘typical’ or TT library, while extreme process values are captured in 4 corner libraries called FF, SS, FS, and SF (referring to fast NMOS and PMOS, slow N and P, fast N/slow P, and slow P/fast N, respectively). The TT model is generated from the measured data on a single golden wafer corresponding to the central-line process. Figure 7.20 describes the data spread from its typical value and position of the corners. Here σ represents the standard deviation calculated from the measured data. Conventionally, the process variability is modeled by the worst case four corners, two each for analog and digital applications. While the SS and FF corners are used for analog circuit modeling, the FS and SF corners utilized for digital circuit generation. The advantage of this design corner approach is that the corner models are supplied to the designers so that the circuits can be simulated at each of the four process corners. But, there are some problems with this approach. The fixed corners tend to be too pessimistic. As illustrated in Fig. 7.20, there are some extreme combinations of process parameters that are too unrealistic. Thus, a corner-based methodology often leads to over design. Moreover, while generating the corner parameters, the correlation between the core model parameters are ignored. Therefore, the design may still work, but it will take a larger die area and more design effort to achieve the same function. This approach therefore, does not provide adequate information about the robustness of the design. It may however, be noted that because of the simplicity of the approach, until recently this is the most common technique used by the designer for estimating the robustness of the design.
Yield Analysis and Optimization
Published in Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 2008
Puneet Gupta, Evanthia Papadopoulou
Traditionally, static timing and power analysis tools have relied on two or more corners of process, voltage, and temperature or PVT. We are not going to discuss operating variations such as voltage fluctuations and temperature gradients here. Timing corners are typically specified as slow (S), typical (T), or fast (F). Thus, SS represents a process corner with slow PFET and slow NFET behavior. The common performance analysis process corners are (TT, SS, FF, SF, FS). Similarly, interconnect parasitics are extracted at multiple (usually two) corners. A more systematic approach to determine interconnect R/C corners is given in Ref. [71]. Usually, hold time violations are checked at the FF corner and setup time violations are checked at the SS corner. Similarly, interconnect parasitics can also have typical, minimum, and maximum values. The rationale for corner-based analyses lies in the fact that ensuring correct operation of the design at the PVT extrema ensures correct operation throughout the process and operation range. This assumption, though not strictly correct, usually holds well in practice. Corner-based analysis enables pessimistic but deterministic analysis and optimization of designs. Most modern physical design algorithms rely on corner-based design being acceptable. Sub-100 nm process issues (especially variability) have led to the following trends in corner-based design analysis and optimization. More corners. As more complicated process effects emerge and as a result of nonmonotone dependence of delay on many of the process parameters, the number of PVT corners at which a design needs to be signed off is increasing.On chip variation (OCV) analysis. To model within-die variation in static timing tools implicitly analyze clock paths and data paths at separate corners [72]. For example, for setup time analysis, the launching clock path may be analyzed at a slow corner while the capturing clock is analyzed at a fast corner and the data path is analyzed at the slow corner. This in essence tries to model the worst-case impact of on chip variation. Additional techniques such as common path pessimism removal (CPPR), which figures out the shared logic between launching and capturing paths to avoid pushing them to different corners, are used to reduce the inherent pessimism in OCV analysis.
A 0.7 pJ/bit, 1.5 Gbps Energy-Efficient Image-Based True Random Number Generator
Published in IETE Journal of Research, 2023
Dhirendra Kumar, Lakshmi Likhitha Mankali, Prasanna Kumar Misra, Manish Goswami
The simulation result demonstrates that the proposed design is less sensitive to process variations as standard deviation is only 45.69n (less than 2%) when 200 samples were considered for the analysis. Further to convince the robustness of proposed design, the impact of technological process inaccuracies and environment variations were analyzed using corner analysis simulation. This analysis determines the worst-case conditions for the design. Hence five possible process corners (tt- typical, ff-fast fast, fs-fast slow, sf- slow fast and ss- slow slow) were analyzed through post-layout simulation. Figure 11 shows that the worst case has been analyzed when transistors have a fast slow process corner at room temperature.