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Components and Devices
Published in Katsuyuki Sakuma, Krzysztof Iniewski, Flexible, Wearable, and Stretchable Electronics, 2020
The simplest implementations of a digital circuit are logic gates. These are the building blocks of all further digital circuits and are an electronic representation of Boolean logic. There are a number of ways to achieve logic gates electronically, the choice of which depends on the available components, in particular the transistor. Common families of logic gates are PMOS, NMOS or CMOS, referring to the use of p-type semiconductor devices, n-type semiconductor devices or combinations of the two (complementary), respectively. Note that the MOS (metal-oxide-semiconductor) acronym is not always technically correct for TFTs; however, the term is still commonly used. PMOS and NMOS logics are simpler to manufacture, at the cost of higher static power dissipation compared to CMOS logic. Due to fabrication and stability challenges, most demonstrated flexible circuits have used either PMOS or NMOS logic. Most logic gates require between one and four transistors. These gates can then be used to construct exponentially more complex circuits, with a corresponding increase in transistor count. Note that designing fault tolerance into a circuit increases the transistor count further. This poses a significant challenge for flexible electronics as it stands today, as obtaining a high yield of consistent devices is difficult.
Power MOSFET
Published in Dorin O. Neacşu, Automotive Power Systems, 2020
The NMOS and PMOS transistors differ from construction perspective. NMOS transistor is built with n-type source and drain and a p-type substrate, while PMOS transistor is built with p-type source and drain and a n-type substrate. In a NMOS transistor, carriers are electrons, while in a PMOS transistor, carriers are holes. When a high positive voltage is applied to the gate, NMOS transistor will conduct, while PMOS transistor will not. Conversely, a negative gate voltage would turn on the PMOS transistor.
Application-Specific Integrated Circuits
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
M. Michael Vai, William S. Song, Brian M. Tyrrell
The pMOS transistor is a complementary device to the nMOS transistor. It is similar to its nMOS counterpart except that it is built by doping p-type dopants into an n-type substrate. In order to avoid latching up, the substrate must be connected to the highest potential in the circuit to avoid p-n junctions from being turned on. A pMOS transistor has a negative threshold voltage (e.g., −0.7 V). The switching conditions of a pMOS transistor are complementary to an nMOS transistor.
Nodal State Comparison-based Dynamic Hold Technique for Low Power OR Gates in Domino Logic
Published in IETE Journal of Research, 2023
Manish Tiwari, Vijayshri Chaurasia
Table 1 shows the widths of transistors used for constructing the proposed circuit. The minimum length of transistors is Lmin=90 nm. The proposed domino circuit works in a typical manner of charging in the precharge phase and discharging in evaluate phase. In order to keep minimal time taken for charging and discharging operations, PMOS are used as pull-up transistors and NMOS are used as pull-down transistors, in their respective pull-up and pull-down networks (PUN and PDN). Width and length affect the current drive of the circuit, in turn, affecting the delay and power consumption. Length for all transistors is L = Lmin = 90 nm. W/L or Aspect Ratio for PMOS and NMOS labelled as Minv-p and Minv-n, respectively, are kept in approx 2.5:1 ratio for optimally balanced current drive to charge both the pull-up and pull-down transistors: W = 3Lmin for Minv-n and W = 8Lmin for Minv-p.