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Combinational and Sequential Design in CMOS
Published in Manoj Kumar Majumder, Vijay Rao Kumbhare, Aditya Japa, Brajesh Kumar Kaushik, Introduction to Microelectronics to Nanoelectronics, 2020
Manoj Kumar Majumder, Vijay Rao Kumbhare, Aditya Japa, Brajesh Kumar Kaushik
In the pseudo-NMOS ratioed logic circuit, the number of transistors required gets reduced. In complementary CMOS, N-input logic requires 2N transistors, but in a pseudo-NMOS logic circuit, the number of transistors required is N + 1. In ratioed logic, the circuit propagation delay and the power dissipation are affected by the size of the transistor, but in complementary CMOS, they are not affected by the size of the transistor. In ratioed logic, it depends upon the ratio of the size of NMOS and PMOS that is why it is known as ratioed logic. The main disadvantage of the pseudo-NMOS logic is the high static power consumption due to the direct path that exists from VDD to GND. We can design possible alternative topologies for ratioed logics that can completely eliminate static currents and provide lower power consumption [7–9].
Digital Circuits
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
John P. Uyemura, Robert C. Chang, Bing J. Sheu
Examples are provided in Figure 8.10. It should be noted that this type of circuit structuring is possible because the drain and source are interchangeable. The main problem that arises in design complex nMOS logic gates is that the circuit requires large driver-to-load ratios to achieve small VOL values. The switching FET arrays collectively act like a driver network that must be designed to have a large overall effective β value. Although parallel-connected MOSFETs are not a problem, the pull-down resistance of series-connected MOSFETs can be large unless the individual aspect ratios are increased. Satisfying this condition requires additional chip area, decreasing the logic density.
CMOS Circuits
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
Eugene John, Shunzo Yamashita, Dejan Marković, Yuichi Kado
Pseudo NMOS is a ratioed logic. That is for the correct operation of the circuit the width-to-length ratios (W/Ls) of the transistors must be carefully chosen. Instead of a combination of active pull-down and pull-up networks, the ratioed logic consists of a pull-down network and a simple load device. The pull-down network realizes the logic function and a PMOS with grounded gate presents the load device, as shown in Fig. 2.11a. The pseudo-NMOS logic style results in a substantial reduction in gate complexity, by reducing the number of transistors required to realize the logic function by almost half. The speed of the pseudo-NMOS circuit is faster than that of static CMOS realization because of smaller parasitic capacitance. One of the main disadvantages of this design style is the increased static power dissipation. This is due to the fact that, at steady state when the output is 0, pseudo-NMOS circuits provide dc current path from VDD to ground. Figure 2.11b shows the realization of a 2-input NAND gate using pseudo-NMOS logic. When the inputs A = 0 and B = 0, both the transistors in the pull-down network will be OFF and the output will be a logic 1. When A = 0 and B = 1, or A = 1 and B = 0, the pull-down network again will be OFF and the output will be logic 1. When A = 1 and B = 1, both transistors in the pull-down network are ON and the output will be a logic 0, which is the expected result of a NAND gate. Figure 2.11c illustrates the pseudo-NMOS realization of a 2-input NOR gate. Another example for the pseudo-NMOS logic realization is given in Fig. 2.11d. This circuit realizes the function Y = (ABC + D)′, and the operation of this logic circuitry can also be explained in a manner explained above.
Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic
Published in International Journal of Electronics, 2023
Lokesh Boggarapu, Sai Pavan Kumar K, Pown M, B Lakshmi
This section explores IG heterojunction TFET-based NAND and NOR logic circuits with Pseudo-derived logic. To reduce power consumption and delay, Pseudo-derived logic circuits are implemented for the first time. The inverter that uses a p-channel device in pull-up has its gate grounded. The n-channel transistor in the pull-down network is given the input signal. This usage of driving the n-channel transistor with the input in pull-down network is called Pseudo logic (Zhao et al., 2009). In CMOS technology, the Pseudo-NMOS logic is the provider of worst-case power consumption. But coming to the case of TFET technology, implementation of this Pseudo logic seems to be a promising logic in reducing the power consumption by making a change in its configuration. In this logic, the PMOS transistor is always turned on and it is in the linear region of operation. This means that as PMOS is always on, the resistance of drain-source would be very less and so the time constant RC is low, thus enhancing the speed of operation. The same has been applied to TFET-based NAND and NOR logic circuits. But this Pseudo logic has been modified in such a way that HPTFET is not permanently connected to the ground but connected to a pulsating signal, which controls the pull-down network. This makes HPTFET turned on only for the half cycle of the control signal.
Parameter extraction and modelling of the MOS transistor by an equivalent resistance
Published in Mathematical and Computer Modelling of Dynamical Systems, 2021
Sherif M. Sharroush, Yasser S. Abdalla
The third case to be considered is that when both the pull-up network (PUN) and the PDN are active. This is the case in the pseudo-NMOS logic-circuit family. Refer to Figure 20 (a) for the inverter in this family. When vin is equal to 0 V, MN is deactivated and the load capacitance, CL, charges to VDD which is the output-high voltage, VOH. If vin is equal to VDD, MN is activated; however, the output-low voltage, VOL, is not equal to 0 V in this case due to the contention current of the always-activated PMOS transistor, MP. In this case, the equivalent circuit is as shown in Figure 20 (b) where RN and RP are the equivalent resistances of MN and MP, respectively. It is now required to find the expressions of RN and RP. Towards that end, the two circuits of Figures 20 (a) and (b) are analysed with the expressions of the high-to-low propagation delay, tPHL, and the fall time, tf, equalized for the two circuits.
Performance Analysis of Multipliers Using Modified Gate Diffused Input Technology
Published in IETE Journal of Research, 2022
Y. G. Praveen Kumar, B. S. Kariyappa, S. M. Shashank, C. N. Bharath
The paper [2] presents a novel approach (viz. GDI) for designing digital circuits for low power applications. Numerous logic functions and digital circuits operating at different voltage levels are implemented in CMOS, PTL, NMOS logic and using transmission gates. All the circuits are implemented in regular p-well CMOS process and comparisons among all the designs are discussed with respect to power, delay and number of devices. Around 45% reduction in power delay product is achieved in GDI-based designs than CMOS-based designs. Also increased performance with reduced delay, power and number of devices was observed in GDI-based circuits over conventional methods.