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Calculate the Force Applied on a Surface Using FSR
Published in Anudeep Juluru, Shriram K. Vasudevan, T. S. Murugesh, fied!, 2023
Anudeep Juluru, Shriram K. Vasudevan, T. S. Murugesh
Remember: In the circuit shown in Figure 5.4, the resistor between the FSR and the GND is known as a pull-down resistor. The higher the value of pull-down resistance, the higher the accuracy of FSR values. Similarly, if a resistor is connected between a sensor and the VCC, then it is known as a pull-up resistor. The lower the value of pull-up resistance, the higher the accuracy of the sensor values. So, a high-value resistor is used between the FSR and GND. If you have a higher value resistor than 10 kΩ, then you can use it as a pull-down resistor and this won’t affect the performance. Refer to Figure 5.5 to better understand the difference between a pull-up and pull-down resistor.
Architecture and Instruction Set
Published in Julio Sanchez, Maria P. Canton, Embedded Systems Circuits and Programming, 2017
Julio Sanchez, Maria P. Canton
The reset mechanism is used to place the PIC in a known condition, to gain control of a run-away or hung-up program, as a forced interrupt in program execution, or to make the device ready at program load time. The processor’s !MCLR pin produces the reset action when it reads logic zero. The exclamation sign preceding the pin’s name (or alternatively, as a line over the text) indicates that the action is active-low. To prevent accidental resets the !MCLR pin must be connected to the positive voltage supply through a 5K or 10K resistor. When a resistor serves to place a logic 1 on a line, it is called a pull-up resistor.
Mid-range PIC Architecture
Published in Julio Sanchez, Maria P. Canton, Microcontroller Programming, 2018
Julio Sanchez, Maria P. Canton
The reset mechanism places the PIC in a known condition. The reset mechanism is used to gain control of a runaway or hung-up program, as a forced interrupt in program execution, or to make the device ready at program load time. The processor’s !MCLR pin produces the reset action when it reads logic zero. The exclamation sign preceding the pin’s name (or a line over it) indicates that the action is active-low. To prevent accidental resets the !MCLR pin must be connected to the positive voltage supply through a 5K or 10K resistor. When a resistor serves to place a logic one on a line it is called a pull-up resistor.
Synergistic effect of enhanced low-dose-rate sensitivity and single event transient in bipolar voltage comparator LM139
Published in Journal of Nuclear Science and Technology, 2019
Shuai Yao, Wu Lu, Xin Yu, Xin Wang, Xiaolong Li, Mohan Liu, Jing Sun, XinYu Wei, YaoDong Chang, Qi Guo, ChengFa He
When the low-level output is biased, the transistors inside the LM139 that are turned on are opposite to the high-level output biasing, as shown in Figure 9. In the initial state, transistor Q5 is off and Q6 is on. The current flowing through the resistor R can make Vout be approximately equal to zero. During pulsed laser testing, Q5 may be turned on. Therefore, the base current flowing through Q6 decreases, which in turn causes the collector current of Q6 to decrease. Meanwhile, the current flowing through the pull-up resistor R decreases, and a transient output is generated. The analysis is based on the transient analysis of the LM139 with high-level output biasing, as described above. The only difference is that the sensitive transistors of the SET change.
Review of Approaches for Radiation Hardened Combinational Logic in CMOS Silicon Technology
Published in IETE Technical Review, 2018
Vaibhav Sharma, Arvind Rajawat
The next technique is based on SEU hardening of logic gates. A simple inverter has one n-channel MOSFET connected to an input and a pull up resistor between its drain and power supply. One n-channel transistor is added which has an active biasing with shunt resistor and has an isolated well with respect to former transistor. This arrangement will create low field transistors. The technique is named as isolated well hardening approach [17]. Finally, the resistors were replaced with p-channel transistors. Test vectors are created using 0.5 µm bulk CMOS process. SPICE simulation results show a hardened inverter has a critical charge enhancement, just double compared with non-hardened. Laser test results show that this hardened inverter gives same performance (but with relative PAD overheads) when thrice times approximate LET is incident on it.
A simple and versatile overcurrent protection circuit for power MOSFETs
Published in International Journal of Electronics, 2019
Praveen V. Pol, Sanjaykumar L. Patil, Sanjeev Kumar Pandey
Thus, the value of can be determined for the required value of . When overcurrent event occurs, discharges , which disables the driver IC, goes low, and then is switched-off. is then released by and re-commence charging via and also by the IC internal pull up resistor , therefore the charging of is from parallel combination of the above resistors. Besides the gate to source capacitance of is parallel with and hence it also charges simultaneously with thereby reducing charging speed of . Thus and also play role in determination of shutdown time. The time required to charge the capacitor to the logic high threshold voltage level of the driver IC, is the driver IC shutdown time which is given by