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Digital Design with Programmable Logic Devices
Published in Suman Lata Tripathi, Sobhit Saxena, Sushanta Kumar Mohapatra, Advanced VLSI Design and Testability Issues, 2020
M. Panigrahy, S. Jena, R. L. Pradhan
In general, a CPLD may be viewed to have a number of logic blocks, a dedicated I/O block and a switch matrix interconnecting them. I/O block consists of I/O elements that provide buffering for the input and output signals. The logic block is formed by several logic elements known as macrocells. A macrocell comprises AND and OR arrays, a dedicated flip-flop, and control signals for implementation of the desired combinatorial or sequential functions. Fast routing between macrocells leads to lower time delays within a logic block. Dedicated global clock lines leverage proper clock distribution among logic blocks and uniform timing properties. The modern CPLDs contain 32–1700 macrocells enabling designers to implement complex logic functions.
FPGAs for Rapid Prototyping
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
Simple programmable logic devices (PLDs), consisting of programmable array logics (PALs) and programmable logic arrays (PLAs), have been in use for over 25 years. Simple PLDs can replace several older fixed function TTL-style parts in a design. Most PLDs contain a series of AND gates with fuse programmable inputs that feed into an array of fuse programmable OR gates. In PALs, the AND array is programmable but the OR array has a fixed input connection. In a PLA or PAL, a series of AND gates feeding into an OR gate are programmed to directly implement a sum-of-products (SOP) Boolean equation. An example of SOP implementation using a PLA can be seen in Figure 9.3. Note that inverters are provided so that every input signal is also available in normal or complemented form. A shorthand notation is used for the gate inputs in PLAs. A PLA's AND and OR gates have inputs where each horizontal and vertical lines cross. Initially in a PLA, all fuses are intact which means that each AND gate performs a logical AND on every input signal and its logical complement. By blowing unwanted fuses or programming, the unwanted AND gate inputs are disconnected by the user and the required product term is produced. In PALs, different devices are selected depending on the number of product terms (i.e., inputs to OR gate) in the SOP logic equation. Some devices have onetime programmable fuses and others have fuses that can be erased and reprogrammed. On many PLDs, the output of the OR gate is connected to a flip-flop whose output can then be fed back as an input into the AND gate array. This provides PLDs with the capability to implement simple state machines. A simple PLD can contain several of these AND/OR networks. The largest product-term devices contain an array of PLAs with a simple interconnection network. This type of device is called a complex programmable logic device (CPLD). Product-term devices typically range in size from several hundred to a few thousand gates.
Outdoor environmental sensitivity test for the detection of biological aerosols
Published in Instrumentation Science & Technology, 2021
Hyunsoo Seo, Kibong Choi, Jinho Park
The signal processing method involves four steps as shown in Figure S1. First, when particles are introduced through the nozzle, scattered light and fluorescence analog signals are acquired by the PMT. Next, for signal amplification, the analog optical signals are converted into voltages, which are supplied as inverting inputs, so that the phase of the output signal of the preamplifier is reversed. The amplification is repeated using an analog front-end amplifier (AD829, Analog Devices, USA). The amplified output voltage-of-fluctuation signals, VFT, are converted into digital signals by comparing them to the threshold voltage, VTHD. The digital signals are counted by varying the digital pulse width with respect to their intensities. Using a digital complex programmable logic device (CPLD; 5M2210ZF256I5N, Altera, USA), the pulse width signals are sampled at 1 MHz, and the device acts as an intermediate, so that, if the logical value is “1,” the signal is counted and sent to the microcontroller unit (MCU; STM32F420, STMicroelectronics, USA).
Source-side low-frequency harmonic suppression method for matrix converter
Published in International Journal of Electronics, 2021
By establishing a system model, the proposed strategy was simulated using Matlab/Simulink to verify the effectiveness of the method. The proposed MC control strategy was experimentally tested using a prototype. A platform was constructed using a digital signal processor (DSP) and a complex programmable logic device (CPLD). The bidirectional switch used in the experiment was obtained by connecting two insulated gate bipolar transistors (IGBT) and two diodes in anti-parallel as shown in Figure 10. In the experimental prototype, Hall voltage and Hall current sensors were used to sample input and output voltages and currents. Damping resistance Rd is connected in parallel with input filter inductance Lf to suppress input current resonance. Table 2 shows the system parameters under the proposed and conventional control strategies. Based on the setting of output asymmetry in Table 2 and (8), the maximum system voltage gain is as follows: . According to the setting of output asymmetry in Table 2 and equation (11), the theoretical values of the third harmonic contents in the input current are as follows: , .
Novel laser induced breakdown spectroscopy – Raman instrumentation using a single pulsed laser and an echelle spectrometer
Published in Instrumentation Science & Technology, 2018
Qingyu Lin, Shuai Wang, Guangmeng Guo, Yonghui Tian, Yixiang Duan
The transmitted beam (90 mJ, 10 Hz) used for the LIBS plasma excitation, was focused on the target surface by composite lens (Throlabs) with a focal length of 100 mm. This part of LIBS laser beam produced a typical irradiance of about 35 MW/mm2. Plasma radiation was collected at a 45° side view relative to the beam using a fiber optic probe (f/2 fused silica lens for 200–2000 nm, 5 mm diameter, 10 mm focal length). The plasma radiation was directly guided into an echelle spectrometer (f/10 aperture ratio, 400 mm focal length, 205–821 nm) equipped with an electron multiplying charge-coupled device detector (Andor Instruments, cooling −75°C), which is 1024 × 1024 pixels with dimensions of 13 × 13 µm. The overall linear dispersion of the spectrometer system ranges from 37 pm (at 220 nm) to 133 pm per pixel (at 800 nm). To prevent the electron multiplying charge-coupled device detection of the early continuum radiation from the LIBS plasma, a mechanical chopper was used in front of the entrance slit, which cut off the initial portion of the plasma radiation. A complex programmable logic device (100 MHz) was used to control the position of the chopper. The temporal precision of the complex programmable logic device was 10 ns. Each recording was obtained by accumulating the signals of 100 ablation events, which can also be helpful for the enhancement of the signal-to-noise ratio.