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Fixed-Point Subtraction
Published in Joseph Cavanagh, Computer Arithmetic and Verilog HDL Fundamentals, 2017
This section presents the design of an 8-bit fixed-point ripple adder/subtractor. The design of a carry lookahead adder/subtractor is similar except that the carry logic uses the carry lookahead technique. It is desirable to have the adder unit perform both addition and subtraction since there is no advantage to having a separate adder and subtractor. A ripple-carry adder will be modified so that it can perform subtraction while still maintaining the ability to add. In order to form the 2s complement from the 1s complement, the carry-in to the low-order stage of the adder will be a 1 if subtraction is to be performed. The logic diagram is shown in Figure 5.1. Overflow is detected if the carries out of bit 6 and bit 7 are different.
Introduction to Mechatronic Systems
Published in Bogdan M. Wilamowski, J. David Irwin, Control and Mechatronics, 2018
In electronics, an arithmetic logic circuit, such as adder, is a digital circuit that performs logical operation of numbers in Boolean logic. In modern computers, arithmetic operators reside in the arithmetic logic unit (ALU), where all operations, such as addition, subtraction, multiplication, and division, are performed. Although an arithmetic logic circuit can be constructed for many numerical representations, such as a binary-coded decimal like excess-3, the most common arithmetic logic circuits operate on binary numbers. In the arithmetic logic circuit, in which two’s complement or one’s complement is used to represent negative numbers, it is trivial to modify an adder into an adder–subtractor.
Advanced Signal Processing Resources in FPGAs
Published in Juan José Rodríguez Andina, Eduardo de la Torre Arnanz, María Dolores Valdés Peña, FPGAs, 2017
Juan José Rodríguez Andina, Eduardo de la Torre Arnanz, María Dolores Valdés Peña
The pre-adder/subtractor may be used as an independent computing resource or to generate one of the input operands of the multiplier. This second alternative is useful for the implementation of some functionalities, for instance, the symmetric filter shown in Figure 4.4.
Fault Resistant Coplanar QCA Full Adder-Subtractor Using Clock Zone-Based Crossover
Published in IETE Journal of Research, 2023
R. Marshal, G. Lakshminarayanan
The clock zone crossover design is realized using (2) and (5) as presented in Figure 4 and the results are presented in Figure 6. If Mode=0, the adder-subtractor will function as an adder and if Mode=1, it will function as a subtractor. The XOR operation is realized by using the Three-Input XOR (TIEO) gate proposed in [7].
A novel efficient coplanar QCA full adder and full subtractor design
Published in International Journal of Electronics, 2023
Radhouane Laajimi, Lamjed Touil, Ali Newaz Bahar
On one hand, conventional Completely Metal Oxide Semiconductors (CMOS) technology based on transistors cannot be minimised significantly to a small size, as compared to their actual dimensions, due to problems with current leakage, which prevents the device from shutting down properly, and because of higher heat dissipation, leading to the risk of chip destruction. Thus, designers have been searching for alternative technology that provide lower energy consumption and higher density used for Arithmetic Logic Unit (ALU) applications for any computer devices. At the same time, the scalability of traditional technology is coming to an end, making it necessary to develop monomolecular devices. The International Technology Roadmap for Semiconductors (ITRS) outlines a number of new nano devices that could correctly replace CMOS technology, including the Carbon Nanotubes (CNT), Single-Electron Transistor (SET), Resonant Tunnelling Diode (RTD), single-electron, with Quantum Dot Cellular Automata (QCA; International Technology Roadmap for Semiconductors, 2011). This last technology is the fastest growing alternative for designing ultra-high density, ultra-low power, ultra-high speed digital circuits that can be reduced to the molecular nanoscale (Lent et al., 1993). This is a rapidly growing nanotechnology which has a high potential to complement and eventually replace the conventional CMOS technology (Angizi et al., 2015; Azghadi et al., 2007; Berzon & Fountain, 1999). In contrast to classical CMOS devices, QCA technology offers binary numbers that reflect electron positions within selected quantum dots. As a result, the QCA design has better performance than CMOS regarding switching speed, device density, and power consumption. In fact, the QCA technology provides complete and fully efficient power dissipation advantages. Moreover, this technology can reach an important switching speed of 10 ps, a high density of 1012 devices/cm2 and a low power dissipation of 100 W/cm2 (Walus et al., 2003). The digital QCA circuit design is exploited for practical uses in the design of low-power devices. One of the most used operations in QCA digital is the Full Adder-Subtractor used in many logic applications including division, subtraction, addition and multiplication (PZ Ahmad et al., 2017; Cho & Swartzlander, 2009). Recently, many researchers have suggested the implementation of adders and Subtractors circuit by using QCA technology. The majority of these conceptions are based on an approach known as gate-based design. For this reason, this approach depends on the utilisation of a majority voter that can operate with large complex circuit designs, and high power consumption. Thus, an optimal Full Adder-Subtractor (FAS) design based on QCA technology allows to design arithmetic logic circuits used for computing.