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Simple System Design Techniques
Published in A. Arockia Bazil Raj, FPGA-Based Embedded System Developer's Guide, 2018
Subtraction is a mathematical operation in which one number is deducted from another to obtain the equivalent quantity. The number from which the other number is to be deducted is called the minuend, and the number subtracted from the minuend is called the subtrahend. In all the operations, each subtrahend bit is deducted from the minuend bit. Similarly to binary addition, a single-bit binary subtraction also has four possible operations, such as (0–1 = 0), (1–0 = 1), (1–1 = 0), and (0–1 = 10–1 = 11). This means that, like decimal subtraction, we can simply subtract a smaller number from a bigger number without borrowing anything as the first three subtractions, whereas in the last case, that is, (0–1), subtraction of “1” from “0” is not possible; hence, we need to get a borrow. Then the “0” becomes “10” (“10”–“1” = 1); thus, the difference is “1” and the borrow is also “1”. Similarly to adder circuits, subtraction circuits are also classified as half and full subtractors. A half subtractor is a combinational circuit that does the subtraction of two bits of binary data. It has two input variables and two output variables that correspond to difference and borrow bits. Binary subtraction is performed by the xor gate and a not with an and gate, as shown in Figure 3.3a, which produces the difference and borrow, respectively. Thus, a half subtractor is designed by an xor gate including an and gate with input (A) complemented before being fed to the and gate [21–25].
A simultaneous all-optical half/full-subtraction strategy using cascaded highly nonlinear fibers
Published in Journal of Modern Optics, 2018
Karamdeep Singh, Gurmeet Kaur, Maninder Lal Singh
A half-subtracter is an elementary computational logic circuit capable of deducting two Boolean digits such as A and B, with either being minuend or subtrahend (5–7). Similarly, a full-subtracter is an extended version of a half-subtracter, which has the ability to subtract three input Boolean logic signals (A, B and C), with inputs A, B and C being minuend, subtrahend and borrow from previous subtraction operation (36). Both half/full-subtracter generate two respective outputs namely: difference and borrow. Conceptually, the full-subtracter can be understood as a cascade arrangement of two half-subtracter blocks and with the help of an additional OR gate (37) as shown in Figure 1.