China
Africa
Explore chapters and articles related to this topic
Gate-Level Modeling
Published in Joseph Cavanagh, ® HDL Digital Design and Modeling, 2017
Example 5.10 A half adder will be designed in this example with delays for both the exclusive-OR gate and the AND gate. Recall that a half adder is a combinational circuit that performs addition on two binary bits and produces two outputs — a sum bit and a carry-out bit. The half adder does not accommodate a carry-in bit. The truth table for a half adder is shown in Table 5.6 and the equations for the sum and carry-out are shown in Equation 5.6. sum=a'b+ab'=a⊕bcarry-out=ab
Sub-System Design
Published in M. Michael Vai, Vlsi Design, 2017
The addition time of a ripple-carry adder can be improved with a modified structure called the carry select adder. It retains the layout regularity of a ripple-carry adder. The principle of a carry select adder is to use one ripple-carry adder to execute an addition assuming that the carry-in is 1. Another ripple-carry adder is used to execute the same addition assuming that the carry-in is 0. The real carry-in computed in a previous stage is used to select one of the two sums with a multiplexer. Fig. 7.4 shows an example of an 8-bit carry select adder with a 4-4 staging. The 4-4 staging specifies that two stages are to be used, each of which performs the addition of 4 bits.
Introduction to Logic Design Using Verilog HDL
Published in Joseph Cavanagh, Verilog HDL Design Examples, 2017
This example will use a combination of built-in primitives and UDPs to design a full adder from two half adders. The truth tables for a half adder and full adder are shown in Table 1.14 and Table 1.15, respectively. A half adder is a combinational circuit that performs the addition of two operand bits and produces two outputs: a sum bit and a carry-out bit. The half adder does not accommodate a carry-in bit. A full adder is a combinational circuit that performs the addition of two operand bits plus a carry-in bit. The carry-in represents the carry-out of the previous lower-order stage. The full adder produces two outputs: a sum bit and a carry-out bit.
VHDL implementation of 16x16 multiplier using pipelined 16x8 modified Radix-4 booth multiplier
Published in International Journal of Electronics, 2023
Radwa M. Tawfeek, Marwa A. Elmenyawi
Much research is done in the area of improving the adder design to increase the speed. Different adder designs have been developed over the years; including the Ripple Carry Adders (RCA), Carry Look Ahead adders (CLA), Carry Select Adders (CSA), and Carry Skip adders (CSK). Agarwal R. et al. (Agarwal et al., 2021) developed an algorithm that reduces the number of bits in the addition operation and hence the multiplication speed for accurate Radix-4 Booth multiplier. Pramod.P. and Shahana.T. K. (Patali & Kassim, 2020) developed two hybrid adder versions to increase the speed of addition and hence the speed of the multiplication process and reduce the power consumption. The first adder version merged the carry skip adder with the ripple carry adder. Adding concatenation and incrementation scheme leads to adder version 2, which provides speed improvement in the cost of adding complexity and area. The work in (Surendran & Antony, 2014) used a redundant adder to achieve low power and fast operation.
Design and comparative analysis of memristor-based transistor-less combinational logic circuits
Published in International Journal of Electronics, 2022
Md Hasan Maruf, Md Shakib Ibne Ashrafi, A. S. M. Shihavuddin, Syed Iftekhar Ali
Full adder is one of the common combination logics in the field of the digital circuit which performs binary addition. Full adder has three inputs: InA, InB, and Cin and produces two outputs: Sum and Cout. In this paper, a memristor-based full adder circuit has been proposed where two XOR gates and one OR gate have been used to complete the design. The XOR gate and OR gate are being designed with MRL logic. The novel feature of this design is that it is made using memristors only, no transistors are used. The overall design uses 14 memristors to complete the full adder which is shown in Figure 4. The output expressions of the full adder are given in Equations (8) and (9).
A High-Speed, Low-Power, and Area-Efficient FGMOS-Based Full Adder
Published in IETE Journal of Research, 2022
Roshani Gupta, Rockey Gupta, Susheel Sharma
A high-performance full adder is one of the core elements in the digital system, which performs many operations like subtraction, multiplication, and division and address calculation. Adders are extensively used circuit elements in VLSI systems such as digital signal-processing architectures, video and image processing, microprocessors, etc. Therefore, enhancing the performance of full adder can enhance the overall system performance [14]. The design of FGMOS-based full adder is shown in Figure 1. Here, MOSFETs M1-M2 and M3-M4 are FGMOS inverters to which input bits A, B, and Cin are capacitively coupled so as to generate voltages VFG1 and VFG2. MOSFETs M5-M6 and M7-M8 form standard CMOS inverters to complement V1 and V2 to produce the sum and carry outputs.