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Performance Analysis of Emerging Low-Power Junctionless Tunnel FETs
Published in Shubham Tayal, Abhishek Kumar Upadhyay, Deepak Kumar, Shiromani Balmukund Rahi, Emerging Low-Power Semiconductor Devices, 2023
G. Lakshmi Priya, M. Venkatesh, S. Preethi, T. Venish Kumar, N. B. Balamurugan
Since the inception of Moore’s law, device scaling has been continuing over the past few decades. Aggressive scaling of MOSFET has led to enormous growth of the IC industry incorporating channel lengths to tens of nanometers. This ongoing reduction was possible after Dennard’s work on scaling [6]. In late 2009, Intel began its production with feature size of be 32 nm. In April 2019, Samsung announced a 5 nm process to their potential customers. Transistor size smaller than 7 nm will experience quantum tunneling effect through the gate dielectric layer. But a research team from Berkeley National Laboratory has created a transistor with a working 1 nm gate length. They strongly believe that with proper choice of materials, there is huge room to shrink our electronics. The key element that changed the perception of many scientists is the replacement of silicon material with molybdenum disulfide (MoS2). This material has immense potential for application in LASERs, LEDs, nanoscale transistors, solar cells, and more. The development of MoS2 has kept Moore’s law still alive and enhanced the performance of nanoelectronics devices.
Nonplanar and 3D Devices and Arrays
Published in Arup Bhattacharyya, Silicon Based Unified Memory Devices and Technology, 2017
Friederich et al. investigated optimization of p+ doped trigate stack design for SONOS NAND arrays for MLC operability and potential extendibility for future technology nodes using SOI trigate CMOS technology [24]. The SOI wafers used were of 50 nm silicon thickness and 100 nm of BOX. The ONO stack design consisted of 3.0 nm of tunnel oxide and 9.0 nm each of trapping nitride and blocking oxide to achieve nearly symmetric memory window of 6 V with Vth of nearly−3 V (erase) and +3 V Vth-high (write). The programming conditions were Vg = ±20 V, at write time of 100 us and erase time of 2 ms. The memory window demonstrated efficient erasing with p+ doped polysilicon compared to n+ doped polysilicon gates yielding symmetric window, tighter Vth distribution of multilevel Vth memory states, and superior disturb immunity due to higher work function of p+ gate providing improved blocking properties of unwanted gate injection of charges. The device structure exhibited excellent retention and endurance for DLS (2bit/cell) operation. The NAND strings were fabricated down to 50 nm gate length at 50 nm feature size (F) with 25 nm Fin width and 35 nm spacing providing word-line feasibility down to 15 nm Fin width in a pitch of 100 nm (2F). The design provided 2F x 2F cell size with 2bit/cell capability. The scalability simulation showed that the design as such is scalable down to F = 32 nm. For sub-30 nm node, inter-string distance between the adjacent Fins has to be reduced and metal gate would be required to offset poly depletion effects. Simulation study demonstrated design feasibility at 15 nm Fin width.
Extreme Ultraviolet Light Lithography for Producing Nanofeatures in Next-Generation Semiconductor Processing
Published in R. Mohan Sankaran, Plasma Processing of Nanomaterials, 2017
Although solutions currently exist to go beyond 32 nm on the International Technology Roadmap for Semiconductors, it is clear that there is a need for a more cost-effective, long-term solution that can be extended to create the sub-32 nm features. Currently, excimer lasers coupled with double patterning and immersion lithography is one possibility, but the cost effectiveness of this technique makes it evident that smaller wavelength lithography sources are required. One of the possible next-generation sources that will enable reduction in wavelength is extreme ultraviolet (EUV) light. With its origins beginning in the 1980s, EUV lithography has been widely researched and presents a possible solution to the problems that exist for expanding to sub-10 nm features [4].
Relative stability of shielded top- and side-contact MLGNR interconnects
Published in International Journal of Electronics Letters, 2021
Vijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder
This research work primarily proposes a novel shielding methodology by placing a jacketed aggressor line with respect to the victim in coupled driver-interconnect-load (DIL) arrangement. Using the novel approach, relative stability is critically analysed for TC-and SC-MLGNRs at 32 nm technology. For a cost-effective and feasible fabrication, this work considers 32 nm technology to investigate the stability issues at global interconnect lengths. An accurate Pi-based network is proposed for the first time in order to account the higher-order functions for an improved stability factor. A unique Pi-type network is considered to improve the accuracy of the aforementioned model that is computationally more accurate over L- or T-type networks (Kumbhare, Paltani, Majumder 2019). In order to have a cost-effective, feasible fabrication process and compatibility with CMOS technology, the proposed work considered 32 nm technology node. However, several challenges, such as process complexity, isolation of interconnects due to close proximity of wires, and requirement of high-resolution lithography, etc., are the primary issues due to further scaling of technology lower than 32 nm. Therefore, this work considers 32 nm technology to investigate the shieling approach for TC- and SC-MLGNRs at global interconnect lengths.
Compact AC Modeling of Eddy Current for Cylindrical Through Silicon Via
Published in IETE Journal of Research, 2021
Chopali Chanchal Sahu, Vijay Rao Kumbhare, Manoj Kumar Majumder
This paper for the first time proposed a transmission line model by considering the impact of eddy current at high frequencies. Due to the electromagnetic field generation, the eddy current primarily circulates at the depletion layer, Si substrate, and the neighboring TSVs. Therefore, an eddy resistance comes into existence due to the flow of the eddy current in the conducting material and substrate at high frequencies. In order to address this effect, a closed-form expression is derived for the eddy resistance in the substrate, depletion region, and neighboring TSVs. The MOS (metal oxide semiconductor) effect is taken into the consideration during RLGC modeling of the TSV. The TSV structure comprises filler material surrounded by a liner, depletion layer, and the silicon substrate. The liner and depletion layers are used to prevent the leakage from the TSV to the substrate that provides isolation between the coupled vias. A micro-bump is used as a connector to provide a contact to the TSV with the functional block of the dies. An underfilled layer is used to isolate the bumps from each other to reduce the leakage between them. An IMD layer comprising of metal–oxide is used to separate the bumps from the silicon substrate. Using a three-coupled driver-via-load (DVL) setup, the proposed model is used to analyze the propagation delay under the influence of in-phase and out-of-phase crosstalk. The transmission line model primarily comprises a 20-distributed pi type network driven by a CMOS driver at 32 nm technology. For this research work, 32 nm technology is considered because of its smooth fabrication process and compatibility with the CMOS technology [14]. However, several challenges are introduced with scaling down the technology below 32 nm, such as closer proximity of the TSVs and ultra-high-resolution lithography requirements. With an increase in the TSV density, the impact of cross-coupling capacitance is more severe and becomes a challenging task to isolate from each other. As a result of these, the performance of the overall system degrades [15]. On the other hand, the physical dimension below 32 nm requires a complex process during the fabrication that is costly and requires ultra-high-resolution lithography. Therefore, the performance of TSV is analyzed in terms of delay at 32 nm technology due to its feasible and cost-effective fabrication approach [16].